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hitachi single-chip microcomputer h8/3802 series h8/3802 hd6473802, hd6433802 h8/3801 HD6433801 h8/3800 hd6433800 hardware manual ade-602-203a rev. 2.0 1/9/01 hitachi ltd.
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list of items revised or added for this version section page item description 1.1 overview 3 table 1.1 features description of time specification amended 2.8.1 memory map 46 figure 2.16(2) h8/3801 memory map figure amended 47 figure 2.16(3) h8/3800 memory map figure amended 3.3.1 overview 60 table 3.2 interrupt sources and their priorities amended 3.3.2 interrupt control registers 61 table 3.3 interrupt control registers initial values amended 1. irq edge select register (iegr) bits 4 to 2 amended 62 2. interrupt enable register 1 (ienr1) bits 6, 4, and 3 amended 63 to 65 3. interrupt enable register 2 (ienr2) bits 5, 4, and 1 amended 65 4. interrupt request register 1 (irr1) bits 6, 4, and 3 amended 67, 68 5. interrupt request register 2 (irr2) bits 5, 4, and 1 amended 3.3.5 interrupt operations 74 figure 3.3 flow up to interrupt acceptance figure amended 3.4.2 notes on rewriting port mode registers 79 table 3.5 conditions under which interrupt request flag is set to 1 irrec2 flag condition amended 3.4.3 interrupt request flag clearing methods 80 3.4.3 interrupt request flag clearing method description added 4.5 note on oscillators 90 to 92 4.5.1 definition of oscillation setting standby time 4.5.2 notes on use of crystal oscillator element(excluding ceramic oscillator element) description added 5.1 overview 95 table 5.2 internal state in each operating mode note 7 amended 5.3.3 oscillator setting time after standby mode is cleared 103 table 5.4 clock frequency and setting time changed
section page item description 5.5.2 clearing subsleep mode 108 ? clearing by interrupt description amended 5.6 subactive mode 109 5.6.1 transition to subactive mode description amended 6.3.1 writing and verifying 122 figure 6.4 high-speed,high- reliability programming flow chart write time t opw amended 8.1 overview 131, 132 table 8.1 port functions other function of port 3 and description of port 9 amended 8.2.2 register configuration and description 133 table 8.2 port 3 registers amended and register added 134 1. port data register 3 (pdr3) bit 0 and description amended 2. port control register 3 (pcr3) bit 0 and description amended 3. port pull-up control register 3 (pucr3) bit 0 and description amended 135, 136 4. port mode register 3 (pmr3) bits 5 to 3 and 0, and description amended 136 5. port mode register 2 (pmr2) added 8.3.2 register configuration and description 139 table 8.5 port 4 register initial value amended 140, 141 3. port mode register 2 (pmr2) bits 2 and 1, and description amended 8.3.3 pin functions 141 table 8.6 port 4 pin functions description amended 8.7.2 register configuration and description 155 table 8.17 port 8 registers initial value amended 156 1. port data register 8 (pdr8) bits 7 to 1 amended 2. port control register 8 (pcr8) bits 7 to 1 amended 8.8 port 9 158 8.8.1 overview description amended 8.8.2 register configuration and description table 8.20 port 9 registers initial value amended 159 2. port mode register 9 (pmr9) bit 2 amended, description added, and note changed 8.10.2 register configuration and description 165 table 8.26 port b register initial values added
section page item description 8.11.2 register configuration and descriptions 168, 169 serial port control register (spcr) bits 4, 1, and 0, and description amended 8.12 application note 170 8.12.1 how to handle an unused pin description added 9.1 overview 171 table 9.1 timer functions internal clock of asynchronous event counter amended 9.2.1 overview 174 table 9.2 timer a registers initial value amended 9.2.2 register descriptions 174 1. timer mode register a (tma) bits 7 to 5 amended 9.2.5 application note 178 9.2.5 application note description added 9.3.4 operation 192 1. timer f operation a. operation in 16-bit timer mode description amended 9.3.5 application note 196, 197 3. clear timer fh, timer fl interrupt request flags (irrtfh, irrtfl), timer overflow flags h, l (ovfh, ovfl) and compare match flags h, l (cmfh, cmfl) 4. timer counter (tcf) read/write description added 9.4.2 register configurations 202 5. input pin edge selection register (aegsr) bit name amended 204 6. event counter control register (eccr) bit name, r/w form, and description amended 205 7. event counter control/status register (eccsr) bit name, r/w form, and description amended 10.1.4 register configuration 220 table 10.2 registers initial value of serial port control register amended 10.2 register descriptions 227 10.2.6 serial control register 3 (scr3) description of bit 5 amended 240 10.2.10 serial port control register (spcr) bits 4, 1, and 0, and description amended 12.2 register descriptions 286, 287 12.2.2 a/d mode register (amr) bit 6 amended 12.6 application notes 294 12.6 application notes 4th note added 13.1.4 register configuration 297 table 13.2 lcd controller/driver registers initial values amended
section page item description 13.2 register descriptions 298 13.2.1 lcd port control register (lpcr) bit 4 amended 302 13.2.3 lcd control register 2 (lcr2) bits 4 to 0 amended 14.1 h8/3802 series absolute maximum ratings 313 table 14.1 absolute maximum ratings input voltage amended 14.2.2 dc characteristics 318 to 321 table 14.2 dc characteristics added and amended 14.2.3 ac characteristics 323 table 14.3 control signal timing amended 14.2.4 a/d converter characteristics 325 table 14.5 a/d converter characteristics test conditions amended 14.3 operation timing 329 figure 14.5 sci3 synchronous mode input/output timing reference figure in note amended 14.6 usage note 331 14.6 usage note added b.2 functions 356 spcr initial values and r/w forms amended 357 aegsr r/w form of bit 0 amended 358 eccr r/w form of bit 0 amended 359 eccsr r/w form of bit 5 amended 366 tma initial values and r/w forms of bits 7 to 5 amended 368 tcrf description of bits 6 to 4 amended 371 lpcr initial value and r/w form of bit 4 amended 372 lcr description of bits 3 to 0 amended 373 lcr2 initial values and r/w forms of bits 4 to 0 amended 374 amr initial value and r/w form of bit 6 amended 375 adrrh r/w forms amended 376 pmr2 initial values and r/w forms amended 377 pmr3 r/w forms amended
section page item description b.2 functions 380 pdr3 initial value amended and description added pdr4 descriptions added 381 pdr5 description added pdr6 description added pdr7 description added pdr8 initial values amended and description added 382 pdr9 description added pdra description added pdrb description added pucr3 initial value and r/w form amended 383 pcr3 initial value and r/w form amended 385 pcr8 initial values and r/w forms amended pmr9 initial value and r/w form of bit 2 amended 386 pcra initial values of bits 7 to 4 amended pmrb initial values of bits 7 to 4 and 2 to 0 amended 389 iegr initial values and r/w forms of bits 7, 4 to 2 and description of bit 1 amended 390 ienr1 initial values and r/w forms of bits 6, 4, and 3 amended 391 ienr2 initial values and r/w forms of bits 5, 4, and 1 amended 392 irr1 initial values and r/w forms of bits 6, 4, and 3 amended 393 irr2 initial values and r/w forms of bits 5, 4, and 1 amended
section page item description c.1 block diagrams of port 3 398 figure c.1(b) port 3 block diagram (pin p3 5 ) added 399 figure c.1(c) port 3 block diagram (pins p3 4 and p3 3 ) pin p3 5 deleted c.7 block diagrams of port 9 409 figure c.7(a) port 9 block diagram (pins p9 1 and p9 0 ) figure amended
preface the h8/300l series of single-chip microcomputers has the high-speed h8/300l cpu at its core, with many necessary peripheral functions on-chip. the h8/300l cpu instruction set is compatible with the h8/300 cpu. the h8/3802 series has a system-on-a-chip architecture that includes such peripheral functions as an lcd controller/driver, three timers, a two-channel 10-bit pwm, a serial communication interface, and an a/d converter. this allows h8/3802 series devices to be used as embedded microcomputers in systems requiring lcd display. this manual describes the hardware of the h8/3802 series. for details on the h8/3802 series instruction set, refer to the h8/300l series programming manual.

i contents section 1 overview .............................................................................................................. 1 1.1 overview................................................................................................................... ......... 1 1.2 internal block diagram..................................................................................................... .5 1.3 pin arrangement and functions......................................................................................... 6 1.3.1 pin arrangement ................................................................................................... 6 1.3.2 pin functions ........................................................................................................ 8 section 2 cpu ........................................................................................................................ 11 2.1 overview................................................................................................................... ......... 11 2.1.1 features ................................................................................................................. 11 2.1.2 address space....................................................................................................... 12 2.1.3 register configuration.......................................................................................... 12 2.2 register descriptions ...................................................................................................... ... 13 2.2.1 general registers.................................................................................................. 13 2.2.2 control registers .................................................................................................. 13 2.2.3 initial register values .......................................................................................... 14 2.3 data formats............................................................................................................... ....... 15 2.3.1 data formats in general registers ....................................................................... 16 2.3.2 memory data formats.......................................................................................... 17 2.4 addressing modes........................................................................................................... ... 18 2.4.1 addressing modes ................................................................................................ 18 2.4.2 effective address calculation .............................................................................. 20 2.5 instruction set ............................................................................................................ ........ 24 2.5.1 data transfer instructions .................................................................................... 26 2.5.2 arithmetic operations .......................................................................................... 28 2.5.3 logic operations .................................................................................................. 29 2.5.4 shift operations .................................................................................................... 29 2.5.5 bit manipulations ................................................................................................. 31 2.5.6 branching instructions.......................................................................................... 35 2.5.7 system control instructions.................................................................................. 37 2.5.8 block data transfer instruction............................................................................ 38 2.6 basic operational timing .................................................................................................. 4 0 2.6.1 access to on-chip memory (ram, rom) ......................................................... 40 2.6.2 access to on-chip peripheral modules................................................................ 41 2.7 cpu states ................................................................................................................. ........ 43 2.7.1 overview............................................................................................................... 43 2.7.2 program execution state ...................................................................................... 44 2.7.3 program halt state................................................................................................ 44 2.7.4 exception-handling state ..................................................................................... 44
ii 2.8 memory map................................................................................................................. ..... 45 2.8.1 memory map ........................................................................................................ 45 2.9 application notes .......................................................................................................... .... 48 2.9.1 notes on data access ........................................................................................... 48 2.9.2 notes on bit manipulation.................................................................................... 50 2.9.3 notes on use of the eepmov instruction ........................................................... 56 section 3 exception handling .......................................................................................... 57 3.1 overview................................................................................................................... ......... 57 3.2 reset...................................................................................................................... ............. 57 3.2.1 overview............................................................................................................... 57 3.2.2 reset sequence ..................................................................................................... 57 3.2.3 interrupt immediately after reset ......................................................................... 59 3.3 interrupts ................................................................................................................. ........... 59 3.3.1 overview............................................................................................................... 59 3.3.2 interrupt control registers ................................................................................... 61 3.3.3 external interrupts ................................................................................................ 70 3.3.4 internal interrupts.................................................................................................. 71 3.3.5 interrupt operations.............................................................................................. 72 3.3.6 interrupt response time....................................................................................... 77 3.4 application notes .......................................................................................................... .... 78 3.4.1 notes on stack area use ...................................................................................... 78 3.4.2 notes on rewriting port mode registers ............................................................. 79 3.4.3 interrupt request flag clearing method .............................................................. 80 section 4 clock pulse generators .................................................................................... 83 4.1 overview................................................................................................................... ......... 83 4.1.1 block diagram...................................................................................................... 83 4.1.2 system clock and subclock.................................................................................. 83 4.2 system clock generator .................................................................................................... 8 4 4.3 subclock generator......................................................................................................... ... 87 4.4 prescalers ................................................................................................................. .......... 89 4.5 note on oscillators ........................................................................................................ .... 90 4.5.1 definition of oscillation settling standby time .................................................. 90 4.5.2 notes on use of crystal oscillator element (excluding ceramic oscillator element).............................................................. 92 section 5 power-down modes ......................................................................................... 93 5.1 overview................................................................................................................... ......... 93 5.1.1 system control registers...................................................................................... 96 5.2 sleep mode ................................................................................................................. ....... 101 5.2.1 transition to sleep mode...................................................................................... 101 5.2.2 clearing sleep mode ............................................................................................ 101
iii 5.2.3 clock frequency in sleep (medium-speed) mode .............................................. 102 5.3 standby mode ............................................................................................................... ..... 102 5.3.1 transition to standby mode.................................................................................. 102 5.3.2 clearing standby mode ........................................................................................ 102 5.3.3 oscillator settling time after standby mode is cleared...................................... 103 5.3.4 standby mode transition and pin states.............................................................. 104 5.3.5 notes on external input signal changes before/after standby mode.................. 105 5.4 watch mode ................................................................................................................. ...... 107 5.4.1 transition to watch mode .................................................................................... 107 5.4.2 clearing watch mode ........................................................................................... 107 5.4.3 oscillator settling time after watch mode is cleared ........................................ 107 5.4.4 notes on external input signal changes before/after watch mode..................... 107 5.5 subsleep mode .............................................................................................................. ..... 108 5.5.1 transition to subsleep mode ................................................................................ 108 5.5.2 clearing subsleep mode ....................................................................................... 108 5.6 subactive mode............................................................................................................. ..... 109 5.6.1 transition to subactive mode............................................................................... 109 5.6.2 clearing subactive mode...................................................................................... 109 5.6.3 operating frequency in subactive mode ............................................................. 109 5.7 active (medium-speed) mode .......................................................................................... 110 5.7.1 transition to active (medium-speed) mode........................................................ 110 5.7.2 clearing active (medium-speed) mode .............................................................. 110 5.7.3 operating frequency in active (medium-speed) mode ...................................... 110 5.8 direct transfer ............................................................................................................ ....... 111 5.8.1 overview of direct transfer................................................................................. 111 5.8.2 direct transition times........................................................................................ 112 5.8.3 notes on external input signal changes before/after direct transition.............. 114 5.9 module standby mode....................................................................................................... 1 15 5.9.1 setting module standby mode ............................................................................. 115 5.9.2 clearing module standby mode........................................................................... 115 section 6 rom ...................................................................................................................... 117 6.1 overview................................................................................................................... ......... 117 6.1.1 block diagram...................................................................................................... 117 6.2 h8/3802 prom mode ....................................................................................................... 118 6.2.1 setting to prom mode ........................................................................................ 118 6.2.2 socket adapter pin arrangement and memory map ........................................... 118 6.3 h8/3802 programming....................................................................................................... 1 21 6.3.1 writing and verifying........................................................................................... 121 6.3.2 programming precautions..................................................................................... 126 6.4 reliability of programmed data ........................................................................................ 127
iv section 7 ram ...................................................................................................................... 129 7.1 overview................................................................................................................... ......... 129 7.1.1 block diagram...................................................................................................... 129 section 8 i/o ports ............................................................................................................... 131 8.1 overview................................................................................................................... ......... 131 8.2 port 3..................................................................................................................... ............. 133 8.2.1 overview............................................................................................................... 13 3 8.2.2 register configuration and description ............................................................... 133 8.2.3 pin functions ........................................................................................................ 137 8.2.4 pin states .............................................................................................................. 1 38 8.2.5 mos input pull-up............................................................................................... 138 8.3 port 4..................................................................................................................... ............. 139 8.3.1 overview............................................................................................................... 13 9 8.3.2 register configuration and description ............................................................... 139 8.3.3 pin functions ........................................................................................................ 141 8.3.4 pin states .............................................................................................................. 1 42 8.4 port 5..................................................................................................................... ............. 143 8.4.1 overview............................................................................................................... 14 3 8.4.2 register configuration and description ............................................................... 143 8.4.3 pin functions ........................................................................................................ 146 8.4.4 pin states .............................................................................................................. 1 47 8.4.5 mos input pull-up............................................................................................... 147 8.5 port 6..................................................................................................................... ............. 148 8.5.1 overview............................................................................................................... 14 8 8.5.2 register configuration and description ............................................................... 148 8.5.3 pin functions ........................................................................................................ 150 8.5.4 pin states .............................................................................................................. 1 51 8.5.5 mos input pull-up............................................................................................... 151 8.6 port 7..................................................................................................................... ............. 152 8.6.1 overview............................................................................................................... 15 2 8.6.2 register configuration and description ............................................................... 152 8.6.3 pin functions ........................................................................................................ 154 8.6.4 pin states .............................................................................................................. 1 54 8.7 port 8..................................................................................................................... ............. 155 8.7.1 overview............................................................................................................... 15 5 8.7.2 register configuration and description ............................................................... 155 8.7.3 pin functions ........................................................................................................ 157 8.7.4 pin states .............................................................................................................. 1 57 8.8 port 9..................................................................................................................... ............. 158 8.8.1 overview............................................................................................................... 15 8 8.8.2 register configuration and description ............................................................... 158 8.8.3 pin functions ........................................................................................................ 160
v 8.8.4 pin states .............................................................................................................. 1 60 8.9 port a ..................................................................................................................... ............ 161 8.9.1 overview............................................................................................................... 16 1 8.9.2 register configuration and description ............................................................... 161 8.9.3 pin functions ........................................................................................................ 163 8.9.4 pin states .............................................................................................................. 1 64 8.10 port b .................................................................................................................... ............. 165 8.10.1 overview............................................................................................................... 1 65 8.10.2 register configuration and description ............................................................... 165 8.10.3 pin functions ........................................................................................................ 167 8.11 input/output data inversion function ............................................................................... 168 8.11.1 overview............................................................................................................... 1 68 8.11.2 register configuration and descriptions.............................................................. 168 8.11.3 note on modification of serial port control register.......................................... 169 8.12 application note........................................................................................................... ..... 170 8.12.1 how to handle an unused pin.............................................................................. 170 section 9 timers ................................................................................................................... 171 9.1 overview................................................................................................................... ......... 171 9.2 timer a.................................................................................................................... .......... 172 9.2.1 overview............................................................................................................... 17 2 9.2.2 register descriptions............................................................................................ 174 9.2.3 timer operation.................................................................................................... 177 9.2.4 timer a operation states ..................................................................................... 177 9.2.5 application note................................................................................................... 178 9.3 timer f.................................................................................................................... ........... 178 9.3.1 overview............................................................................................................... 17 8 9.3.2 register descriptions............................................................................................ 181 9.3.3 cpu interface........................................................................................................ 189 9.3.4 operation .............................................................................................................. 19 2 9.3.5 application notes ................................................................................................. 195 9.4 asynchronous event counter (aec)................................................................................. 198 9.4.1 overview............................................................................................................... 19 8 9.4.2 register configurations ........................................................................................ 201 9.4.3 operation .............................................................................................................. 21 0 9.4.4 asynchronous event counter operation modes .................................................. 214 9.4.5 application notes ................................................................................................. 215 section 10 serial communication interface ................................................................. 217 10.1 overview.................................................................................................................. .......... 217 10.1.1 features ................................................................................................................ . 217 10.1.2 block diagram....................................................................................................... 219 10.1.3 pin configuration .................................................................................................. 220
vi 10.1.4 register configuration .......................................................................................... 220 10.2 register descriptions ..................................................................................................... .... 221 10.2.1 receive shift register (rsr) ................................................................................. 221 10.2.2 receive data register (rdr) ................................................................................. 221 10.2.3 transmit shift register (tsr)................................................................................ 222 10.2.4 transmit data register (tdr)................................................................................ 222 10.2.5 serial mode register (smr) .................................................................................. 223 10.2.6 serial control register 3 (scr3)............................................................................ 226 10.2.7 serial status register (ssr) ................................................................................... 230 10.2.8 bit rate register (brr).......................................................................................... 234 10.2.9 clock stop register 1 (ckstpr1) ........................................................................ 239 10.2.10 serial port control register (spcr) .................................................................... 240 10.3 operation................................................................................................................. ........... 241 10.3.1 overview............................................................................................................... 2 41 10.3.2 operation in asynchronous mode........................................................................ 245 10.3.3 operation in synchronous mode .......................................................................... 254 10.3.4 multiprocessor communication function ............................................................ 261 10.4 interrupts ................................................................................................................ ............ 268 10.5 application notes ......................................................................................................... ..... 269 section 11 10-bit pwm ...................................................................................................... 275 11.1 overview.................................................................................................................. .......... 275 11.1.1 features ................................................................................................................ . 275 11.1.2 block diagram...................................................................................................... 276 11.1.3 pin configuration.................................................................................................. 276 11.1.4 register configuration.......................................................................................... 277 11.2 register descriptions ..................................................................................................... .... 278 11.2.1 pwm control register (pwcrm) ....................................................................... 278 11.2.2 pwm data registers u and l (pwdrum, pwdrlm)...................................... 279 11.2.3 clock stop register 2 (ckstpr2) ...................................................................... 279 11.3 operation................................................................................................................. ........... 281 11.3.1 operation .............................................................................................................. 2 81 11.3.2 pwm operation modes........................................................................................ 282 section 12 a/d converter .................................................................................................. 283 12.1 overview.................................................................................................................. .......... 283 12.1.1 features ................................................................................................................ . 283 12.1.2 block diagram...................................................................................................... 284 12.1.3 pin configuration.................................................................................................. 285 12.1.4 register configuration.......................................................................................... 285 12.2 register descriptions ..................................................................................................... .... 286 12.2.1 a/d result registers (adrrh, adrrl) ........................................................... 286 12.2.2 a/d mode register (amr) .................................................................................. 286
vii 12.2.3 a/d start register (adsr) .................................................................................. 288 12.2.4 clock stop register 1 (ckstpr1) ...................................................................... 289 12.3 operation................................................................................................................. ........... 290 12.3.1 a/d conversion operation ................................................................................... 290 12.3.2 a/d converter operation modes.......................................................................... 290 12.4 interrupts ................................................................................................................ ............ 291 12.5 typical use ............................................................................................................... ......... 291 12.6 application notes ......................................................................................................... ..... 294 section 13 lcd controller/driver .................................................................................. 295 13.1 overview.................................................................................................................. .......... 295 13.1.1 features ................................................................................................................ . 295 13.1.2 block diagram...................................................................................................... 296 13.1.3 pin configuration.................................................................................................. 297 13.1.4 register configuration.......................................................................................... 297 13.2 register descriptions ..................................................................................................... .... 298 13.2.1 lcd port control register (lpcr)...................................................................... 298 13.2.2 lcd control register (lcr)................................................................................ 300 13.2.3 lcd control register 2 (lcr2) .......................................................................... 302 13.2.4 clock stop register 2 (ckstpr2) ...................................................................... 303 13.3 operation................................................................................................................. ........... 304 13.3.1 settings up to lcd display.................................................................................. 304 13.3.2 relationship between lcd ram and display .................................................... 306 13.3.3 operation in power-down modes ........................................................................ 311 13.3.4 boosting the lcd drive power supply................................................................ 312 section 14 electrical characteristics .............................................................................. 313 14.1 h8/3802 series absolute maximum ratings .................................................................... 313 14.2 h8/3802 series electrical characteristics.......................................................................... 314 14.2.1 power supply voltage and operating range ....................................................... 314 14.2.2 dc characteristics ................................................................................................ 316 14.2.3 ac characteristics ................................................................................................ 322 14.2.4 a/d converter characteristics.............................................................................. 325 14.2.5 lcd characteristics.............................................................................................. 327 14.3 operation timing .......................................................................................................... ..... 328 14.4 output load circuit ....................................................................................................... .... 330 14.5 resonator equivalent circuit ............................................................................................. 3 30 14.6 usage note ................................................................................................................ ......... 331 appendix a cpu instruction set .................................................................................... 333 a.1 instructions............................................................................................................... .......... 333 a.2 operation code map......................................................................................................... . 341 a.3 number of execution states .............................................................................................. 343
viii appendix b internal i/o registers .................................................................................. 349 b.1 addresses .................................................................................................................. ......... 349 b.2 functions.................................................................................................................. .......... 353 appendix c i/o port block diagrams ........................................................................... 397 c.1 block diagrams of port 3 .................................................................................................. 3 97 c.2 block diagrams of port 4 .................................................................................................. 4 01 c.3 block diagram of port 5 .................................................................................................... 405 c.4 block diagram of port 6 .................................................................................................... 406 c.5 block diagram of port 7 .................................................................................................... 407 c.6 block diagrams of port 8 .................................................................................................. 4 08 c.7 block diagrams of port 9 .................................................................................................. 4 09 c.8 block diagram of port a ................................................................................................... 4 10 c.9 block diagram of port b ................................................................................................... 4 11 appendix d port states in the different processing states ..................................... 412 appendix e list of product codes .................................................................................. 413 appendix f package dimensions .................................................................................... 414
1 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3802 series comprises single-chip microcomputers equipped with a controller/driver. other on-chip peripheral functions include three timers, a two-channel 10-bit pulse width modulator (pwm), a serial communication interface, and an a/d converter. together, these functions make the h8/3800 series ideally suited for embedded applications in systems requiring low power consumption and lcd display. models in the h8/3802 series are the h8/3802, with on-chip 16-kbyte rom and 1-kbyte ram, the h8/3801, with 12-kbyte rom and 512 byte ram, and the h8/3800, with 8-kbyte rom and 512 byte ram. the h8/3802 is also available in a ztat* version with on-chip prom which can be programmed as required by the user. table 1.1 summarizes the features of the h8/3802 series. note: * ztat (zero turn around time) is a trademark of hitachi, ltd.
2 table 1.1 features item specification cpu high-speed h8/300l cpu ? general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) ? operating speed ? max. operating speed: 8 mhz ? add/subtract: 0.25 ? (operating at 8 mhz) ? multiply/divide: 1.75 ? (operating at 8 mhz) ? can run on 32.768 khz or 38.4 khz subclock ? instruction set compatible with h8/300 cpu ? instruction length of 2 bytes or 4 bytes ? basic arithmetic operations between registers ? mov instruction for data transfer between memory and registers ? typical instructions ? multiply (8 bits 8 bits) ? divide (16 bits 8 bits) ? bit accumulator ? register-indirect designation of bit position interrupts 18 interrupt sources ? 11 external interrupt sources (irq 1 , irq 0 , wkp 7 to wkp 0 , irqaec) ? 7 internal interrupt sources clock pulse generators two on-chip clock pulse generators ? system clock pulse generator: 1.0 to 16 mhz ? subclock pulse generator: 32.768 khz, 38.4 khz power-down modes seven power-down modes ? sleep (high-speed) mode ? sleep (medium-speed) mode ? standby mode ? watch mode ? subsleep mode ? subactive mode ? active (medium-speed) mode
3 item specification memory large on-chip memory ? h8/3802: 16-kbyte rom, 1-kbyte ram ? h8/3801: 12-kbyte rom, 512 byte ram ? h8/3800: 8-kbyte rom, 512 byte ram i/o ports 50 pins ? 39 i/o pins ? 5 input pins ? 6 output pins timers three on-chip timers ? timer a: 8-bit timer count-up timer with selection of eight internal clock signals divided from the system clock (? * and four clock signals divided from the watch clock ( w ) * ? asynchronous event counter: 16-bit timer ? count-up timer able to count asynchronous external events independently of the mcu's internal clocks asynchronous external events can be counted (both rising and falling edge detection possible) ? timer f: 16-bit timer ? can be used as two independent 8-bit timers ? count-up by an event input from the four internal clocks ? provision for toggle output by means of compare-match function serial communication interface ? sci3: 8-bit synchronous/asynchronous serial interface incorporates multiprocessor communication function 10-bit pwm pulse-division pwm output for reduced ripple ? can be used as a 10-bit d/a converter by connecting to an external low-pass filter. a/d converter successive approximations using a resistance ladder ? 4-channel analog input pins ? conversion time: 31/?or 62/? per channel
4 item specification lcd controller/driver lcd controller/driver equipped with a maximum of 25 segment pins and four common pins ? choice of four duty cycles (static, 1/2, 1/3, or 1/4) ? segment pins can be switched to general-purpose port function in 4-bit units product lineup product code mask rom version ztat version package rom/ram size hd6433802h hd6473802h 64-pin qfp (fp-64a) rom 16 kbytes hd6433802fp hd6473802fp 64-pin lqfp (fp-64e) ram 1 kbytes hd6433802p hd6473802p 64-pin dilp (dp-64s) HD6433801h 64-pin qfp (fp-64a) rom 12 kbytes HD6433801fp 64-pin lqfp (fp-64e) ram 512 bytes HD6433801p 64-pin dilp (dp-64s) hd6433800h 64-pin qfp (fp-64a) rom 8 kbytes hd6433800fp 64-pin lqfp (fp-64e) ram 512 bytes hd6433800p 64-pin dilp (dp-64s) note: * see section 4, clock pulse generator, for the definition of ?and. w .
5 1.2 internal block diagram figure 1.1 shows a block diagram of the h8/3802 series. sub clock osc h8/300l cpu ram port a port 9 port 8 port 7 port b lcd power supply port 6 port 5 port 4 port 3 system clock osc rom timer - a timer - f asynchronous counter (16 bit) serial communication interface (sci3) 10-bit pwm1 a/d (10 bit) 10-bit pwm2 lcd controller /driver large-current (25 ma/pin) high-voltage open-drain pin (7 v) large-current (10 ma/pin) high-voltage open-drain pin (7 v) high-voltage (7 v) input pin v ss = av ss v cc res test irq wkp wkp wkp wkp wkp wkp wkp wkp irq1 figure 1.1 block diagram
6 1.3 pin arrangement and functions 1.3.1 pin arrangement the h8/3802 series pin arrangement is shown in figures 1.2 and 1.3. p9 0 /pwm1 p9 1 /pwm2 p9 2 p9 3 p9 4 p9 5 v ss irqaec p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / irq irq res wkp wkp wkp wkp wkp wkp wkp wkp 64a, fp 64e (top view) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1.2 pin arrangement (fp-64a, fp-64e: top view)
7 p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / irq irq res wkp0 wkp1 wkp2 wkp3 wkp4 wkp5 wkp6 wkp7 figure 1.3 pin arrangement (dp-64s: top view)
8 1.3.2 pin functions table 1.2 outlines the pin functions of the h8/3802 series. table 1.2 pin functions pin no. type symbol fp-64a fp-64e dp-64s i/o name and functions power source pins v cc 16 24 input power supply: all v cc pins should be connected to the system power supply. v ss 4 (= av ss ) 55 12 (= av ss ) 63 input ground: all v ss pins should be connected to the system power supply (0 v). av cc 61 5 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. av ss 4 (= v ss ) 12 (= v ss ) input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0v). v 1 v 2 v 3 17 18 19 25 26 27 input lcd power supply: these are the power supply pins for the lcd controller/driver. clock pins osc 1 osc 2 6 5 14 13 input output these pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. see section 4, clock pulse generators, for a typical connection diagram. x 1 x 2 2 3 10 11 input output these pins connect to a 32.768-khz or 38.4-khz crystal oscillator. see section 4, clock pulse generators, for a typical connection diagram. system control res
9 pin no. type symbol fp-64a fp-64e dp-64s i/o name and functions interrupt pins irq irq wkp wkp
10 pin no. type symbol fp-64a fp-64e dp-64s i/o name and functions i/o ports p6 7 to p6 0 33 to 40 41 to 48 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 25 to 32 33 to 40 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 0 24 32 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). p9 5 to p9 0 54 to 49 62 to 57 output port 9: this is a 6-bit output port. pa 3 to pa 0 20 to 23 28 to 31 i/o port a: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register a (pcra). pb 3 to pb 0 1, 64 to 62 9 to 6 input port b: this is a 4-bit input port. serial communi- rxd 32 58 2 input sci3 receive data input: this is the sci3 data input pin. cation interface txd 32 59 3 output sci3 transmit data output: this is the sci3 data output pin. (sci) sck 32 57 1 i/o sci3 clock i/o: this is the sci3 clock i/o pin. a/d converter an3 to an0 1 64 to 62 9 to 6 input analog input channels 3 to 0: these are analog data input channels to the a/d converter lcd controller/ com 4 to com 1 20 to 23 28 to 31 output lcd common output: these are the lcd common output pins. driver seg 25 to seg 1 24 to 48 32 to 56 output lcd segment output: these are the lcd segment output pins.
11 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. ? general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers ? instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct ? register indirect ? register indirect with displacement ? register indirect with post-increment or pre-decrement ? absolute address ? immediate ? program-counter relative ? memory indirect ? 64-kbyte address space ? high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations ? 8- or 16-bit register-register add or subtract: 0.25 ?* ? 8 8-bit multiply: 1.75 ?* ? 16 ?8-bit divide: 1.75 ?* note: * these values are at ?= 8 mhz. ? low-power operation modes sleep instruction for transfer to low-power operation
12 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 753210 64 figure 2.1 cpu registers
13 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). condition code register (ccr): this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions.
14 bit 7?nterrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 3.3, interrupts. bit 6?ser bit (u): can be used freely by the user. bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?ser bit (u): can be used freely by the user. bit 3?egative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer should be initialized by software, by the first instruction executed after a reset.
15 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. ? bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). ? all arithmetic and logic instructions except adds and subs can operate on byte data. ? the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits ?8 bits) instructions operate on word data. ? the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit.
16 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 7 6 5 4 3 2 1 0 don? care data type register no. data format 70 1-bit data rnh 76543210 don? care 70 1-bit data rnl msb lsb don? care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl notation: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don? care 70 msb lsb 15 0 upper digit lower digit don? care 70 3 4 don? care upper digit lower digit 70 3 4 figure 2.3 register data formats
17 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. the h8/300l cpu can access word data stored in memory (mov.w instruction), but the word data must always begin at an even address. if word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. the same applies to instruction codes. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register note: ignored on return * figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored.
18 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @ rn 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits) instructions have 16-bit operands. 2. register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement?(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even.
19 4. register indirect with post-increment or pre-decrement?rn+ or @?n: ? @rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. ? @ rn the @ rn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is 126 to +128 bytes ( 63 to +64 words) from the current address. the displacement should be an even number. 8. memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information.
20 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. register indirect (1) (bset, bclr, bnot, and btst instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand.
21 table 2.2 effective address calculation addressing mode and instruction format op rm 76 3 40 15 no. effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn register indirect, @rn contents (16 bits) of register indicated by rm 0 15 register indirect with displacement, @(d:16, rn) op rm rn 87 3 40 15 op rm 76 3 40 15 disp op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @ rn 2 3 4 incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 30 rn 30 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm
22 addressing mode and instruction format no. effective address calculation method effective address (ea) 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 87 0 15 op 0 15 imm op disp 70 15 program-counter relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 87 0 15 0 15 abs op #xx:16 op 87 0 15 imm immediate #xx:8 8 sign extension disp
23 addressing mode and instruction format no. effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 notation: rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address abs
24 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @ sp. pop rn is equivalent to mov.w @sp+, rn. the same applies to the machine language. 2. bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next.
25 notation rd general register (destination) rs general register (source) rn general register (ead), destination operand (eas), source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition subtraction
26 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) rn, and @rn+ addressing modes are available for word data. the @aa:8 addressing mode is available for byte data only. the @ r7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ sp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @ sp. notes: * size: operand size b: byte w: word certain precautions are required in data access. see 2.9.1, notes on data access, for details.
27 15 0 87 op rm rn mov rm rm 15 0 87 op rn abs @aa:8 sp
28 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd ?rs rs 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd rs, rd #imm compares data in a general register with data in another general register or with immediate data, and indicates the result in the ccr. word data can be compared only between two general registers. neg b 0 rd s complement (arithmetic complement) of data in a general register notes: * size: operand size b: byte w: word
29 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd s complement (logical complement) of general register contents notes: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift
30 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) notation: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes
31 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1
32 instruction size * function bxor b c
33 15 0 87 op imm rn operand: bit no.: notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes
34 notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont)
35 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc branches to the designated address if condition cc is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c branches unconditionally to a specified address bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine
36 notation: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes
37 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte returns from an exception-handling routine sleep causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details. ldc b rs pc + 2
38 notation: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov if r4l 1
39 notation: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code
40 2.6 basic operational timing cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub or figure 2.11 on-chip memory access cycle
41 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. figures 2.12 and 2.13 show the on-chip peripheral module access cycle. two-state access to on-chip peripheral modules t 1 state bus cycle t 2 state or internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub figure 2.12 on-chip peripheral module access cycle (2-state access)
42 three-state access to on-chip peripheral modules t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or figure 2.13 on-chip peripheral module access cycle (3-state access)
43 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.14. figure 2.15 shows the state transitions. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep (high-speed) mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized note: see section 5, power-down modes, for details on the modes and their transitions. sleep (medium-speed) mode figure 2.14 cpu operation states
44 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source occurs reset occurs interrupt source occurs exception- handling complete reset occurs figure 2.15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 3.3, interrupts.
45 2.8 memory map 2.8.1 memory map the memory map of the h8/3802 is shown in figure 2.16 (1), that of the h8/3801 in figure 2.16 (2), and that of the h8/3800 in figure 2.16 (3). h'0000 h'0029 h'002a h'3fff h'f740 h'f74c h'fb80 h'ff7f h'ff80 h'ffff interrupt vector area on-chip rom 16 kbytes (16384 bytes) 1024 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (13 bytes) figure 2.16 (1) h8/3802 memory map
46 h'0000 h'0029 h'002a h'2fff h'f740 h'f74c h'fd80 h'ff7f h'ff80 h'ffff interrupt vector area on-chip rom 12 kbytes (12288 bytes) 512 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (13 bytes) figure 2.16 (2) h8/3801 memory map
47 h'0000 h'0029 h'002a h'1fff h'f740 h'f74c h'fd80 h'ff7f h'ff80 h'ffff interrupt vector area on-chip rom 8 kbytes (8192 bytes) 512 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (13 bytes) figure 2.16 (3) h8/3800 memory map
48 2.9 application notes 2.9.1 notes on data access 1. access to empty areas: the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu: unpredictable data is transferred. 2. access to internal i/o registers: internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed.
49 interrupt vector area (42 bytes) on-chip rom 16 kbytes on-chip ram not used not used lcd ram (13 bytes) internal i/o registers (128 bytes) access word byte 2 2 2
50 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o port. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address 1. bit manipulation in two registers assigned to the same address example 1: timer load register and timer counter figure 2.18 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. read write count clock timer counter timer load register reload internal bus figure 2.18 timer configuration example
51 example 2: bset instruction executed designating port 3 p3 7 and p3 6 are designated as input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 1 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p3 1 to high-level output. [a: prior to executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00001 [b: bset instruction executed] bset #1 , @pdr3 the bset instruction is executed designating port 3. [c: after executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level high level pcr3 0 0 1 11111 pdr3 0 1 0 00011 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 3. since p3 7 and p3 6 are input pins, the cpu reads the pin states (low-level and high-level input). p3 5 to p3 1 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'81, but the value read by the cpu is h'41. next, the cpu sets bit 1 of the read data to 1, changing the pdr3 data to h'43. finally, the cpu writes this value (h'43) to pdr3, completing execution of bset. as a result of this operation, bit 1 in pdr3 becomes 1, and p3 1 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. to avoid this problem, store a copy of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3.
52 [a: prior to executing bset] mov. b #81, r0l the pdr3 value (h'81) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pdr3 mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00001 ram0 1 0 0 00001 [b: bset instruction executed] bset #1 , @ram0 the bset instruction is executed designating the pdr3 work area (ram0). [c: after executing bset] mov. b @ram0, r0l the work area (ram0) value is written to pdr3. mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level high level pcr3 0 0 1 11111 pdr3 1 0 0 00011 ram0 1 0 0 00011
53 2. bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 3 control register pcr3 as in the examples above, p3 7 and p3 6 are input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 1 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p3 1 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00001 [b: bclr instruction executed] bclr #1 , @pcr3 the bclr instruction is executed designating pcr3. [c: after executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output output output output output output output input pin state low level high level low level low level low level low level high level pcr3 1 1 1 11101 pdr3 1 0 0 00001 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 1 in the read data to 0, changing the data to h'fd. finally, this value (h'fd) is written to pcr3 and bclr instruction execution ends. as a result of this operation, bit 1 in pcr3 becomes 0, making p3 1 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p3 7 and p3 6 change from input pins to output pins. to avoid this problem, store a copy of the pcr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr3.
54 [a: prior to executing bclr] mov. b #3f, r0l the pcr3 value (h'3f) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level low level pcr3 0 0 1 11111 pdr3 1 0 0 00001 ram0 0 0 1 11111 [b: bclr instruction executed] bclr #1 , @ram0 the bclr instruction is executed designating the pcr3 work area (ram0). [c: after executing bclr] mov. b @ram0, r0l the work area (ram0) value is written to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 input/output input input output output output output output pin state low level high level low level low level low level low level high level pcr3 0 0 1 11101 pdr3 1 0 0 00001 ram0 0 0 1 11101
55 table 2.12 lists the pairs of registers that share identical addresses. table 2.13 lists the registers that contain write-only bits. table 2.12 registers with shared addresses register name abbreviation address port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register a * pdra h'ffdd note: * port data registers have the same addresses as input pins. table 2.13 registers with write-only bits register name abbreviation address port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register a pcra h'ffed timer control register f tcrf h'ffb6 pwm1 control register pwcr1 h'ffd0 pwm1 data register u pwdru1 h'ffd1 pwm1 data register l pwdrl1 h'ffd2 pwm2 control register pwcr2 h'ffcd pwm2 data register u pwdru2 h'ffce pwm2 data register l pwdrl2 h'ffcf
56 2.9.3 notes on use of the eepmov instruction ? ?
57 section 3 exception handling 3.1 overview exception handling is performed in the h8/3802 series when a reset or interrupt occurs. table 3.1 shows the priorities of these two types of exception handling. table 3.1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared low interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence as soon as the res pin goes low, all processing is stopped and the chip enters the reset state. to make sure the chip is reset properly, observe the following precautions. ? at power on: hold the res pin low until the clock pulse generator output stabilizes. ? resetting during operation: hold the res pin low for at least 10 system clock cycles. reset exception handling takes place as follows. ? the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. ? the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc.
58 when system power is turned on or off, the res pin should be held low. figure 3.1 shows the reset sequence starting from res input. vector fetch internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) (1) reset cleared figure 3.1 reset sequence
59 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp). 3.3 interrupts 3.3.1 overview the interrupt sources include 11 external interrupts (wkp 7 to wkp 0 , irq 1 to irq 0 , irqaec) and 7 internal interrupts from on-chip peripheral modules. table 3.2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: ? internal and external interrupts can be masked by the i bit in ccr. when the i bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. ? irqaec, irq 1 to irq 0 , and wkp 7 to wkp 0 can be set to either rising edge sensing or falling edge sensing.
60 table 3.2 interrupt sources and their priorities interrupt source interrupt vector number vector address priority res reset 0 h'0000 to h'0001 high irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irqaec irqaec 6 h'000c to h'000d wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 9 h'0012 to h'0013 timer a timer a overflow 11 h'0016 to h'0017 asynchronous event counter asynchronous event counter overflow 12 h'0018 to h'0019 timer fl timer fl compare match timer fl overflow 14 h'001c to h'001d timer fh timer fh compare match timer fh overflow 15 h'001e to h'001f sci3 sci3 transmit end sci3 transmit data empty sci3 receive data full sci3 overrun error sci3 framing error sci3 parity error 18 h'0024 to h'0025 a/d a/d conversion end 19 h'0026 to h'0027 (sleep instruction executed) direct transfer 20 h'0028 to h'0029 low note: vector addresses h'0002 to h'0007, h'000e to h'0011, h'0014 to h'0015, h'001a to h'001b, and h'0020 to h'0023 are reserved and cannot be used.
61 3.3.2 interrupt control registers table 3.3 lists the registers that control interrupts. table 3.3 interrupt control registers name abbreviation r/w initial value address irq edge select register iegr r/w h'fff2 interrupt enable register 1 ienr1 r/w h'fff3 interrupt enable register 2 ienr2 r/w h'fff4 interrupt request register 1 irr1 r/w * h'fff6 interrupt request register 2 irr2 r/w * h'fff7 wakeup interrupt request register iwpr r/w * h'00 h'fff9 wakeup edge select register wegr r/w h'00 h'ff90 note: * write is enabled only for writing of 0 to clear a flag. 1. irq edge select register (iegr) bit initial value read/write 7 1 6 1 5 1 4 w 3 w 0 ieg0 0 r/w 2 w 1 ieg1 0 r/w iegr is an 8-bit read/write register used to designate whether pins irq 1 and irq 0 are set to rising edge sensing or falling edge sensing. bits 7 to 5: reserved bits bits 7 to 5 are reserved; they are always read as 1 and cannot be modified. bits 4 to 2: reserved bits bits 4 to 2 are reserved; only 0 can be written to these bits.
62 bit 1: irq 1 edge select (ieg1) bit 1 selects the input sensing of the irq 1 pin. bit 1 ieg1 description 0 falling edge of irq irq bit 0: irq 0 edge select (ieg0) bit 0 selects the input sensing of pin irq 0 . bit 0 ieg0 description 0 falling edge of irq irq 2. interrupt enable register 1 (ienr1) bit initial value read/write 7 ienta 0 r/w 6 w 5 ienwp 0 r/w 4 w 3 w 0 ien0 0 r/w 2 ienec2 0 r/w 1 ien1 0 r/w ienr1 is an 8-bit read/write register that enables or disables interrupt requests. bit 7: timer a interrupt enable (ienta) bit 7 enables or disables timer a overflow interrupt requests. bit 7 ienta description 0 disables timer a interrupt requests (initial value) 1 enables timer a interrupt requests bit 6: reserved bit bit 6 is reserved; only 0 can be written to this bit.
63 bit 5: wakeup interrupt enable (ienwp) bit 5 enables or disables wkp 7 to wkp 0 interrupt requests. bit 5 ienwp description 0 disables wkp wkp wkp wkp bits 4 and 3: reserved bits bits 4 and 3 are reserved; only 0 can be written to these bits. bit 2: irqaec interrupt enable (ienec2) bit 2 enables or disables irqaec interrupt requests. bit 2 ienec2 description 0 disables irqaec interrupt requests (initial value) 1 enables irqaec interrupt requests bits 1 and 0: irq 1 and irq 0 interrupt enable (ien1 and ien0) bits 1 and 0 enable or disable irq 1 and irq 0 interrupt requests. bit n ienn description 0 disables interrupt requests from pin irqn irqn 3. interrupt enable register 2 (ienr2) bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 w 4 w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 w ienr2 is an 8-bit read/write register that enables or disables interrupt requests.
64 bit 7: direct transfer interrupt enable (iendt) bit 7 enables or disables direct transfer interrupt requests. bit 7 iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6: a/d converter interrupt enable (ienad) bit 6 enables or disables a/d converter interrupt requests. bit 6 ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bits 5 and 4: reserved bits bits 5 and 4 are reserved; only 0 can be written to these bits. bit 3: timer fh interrupt enable (ientfh) bit 3 enables or disables timer fh compare match and overflow interrupt requests. bit 3 ientfh description 0 disables timer fh interrupt requests (initial value) 1 enables timer fh interrupt requests bit 2: timer fl interrupt enable (ientfl) bit 2 enables or disables timer fl compare match and overflow interrupt requests. bit 2 ientfl description 0 disables timer fl interrupt requests (initial value) 1 enables timer fl interrupt requests
65 bit 1: reserved bit bit 1 is reserved; only 0 can be written to this bit. bit 0: asynchronous event counter interrupt enable (ienec) bit 0 enables or disables asynchronous event counter interrupt requests. bit 0 ienec description 0 disables asynchronous event counter interrupt requests (initial value) 1 enables asynchronous event counter interrupt requests for details of sci3 interrupt control, see 10.2.6. serial control register 3 (scr3). 4. interrupt request register 1 (irr1) bit initial value read/write 7 irrta 0 r/w 6 w 5 1 4 w 3 w 0 irri0 0 r/w 2 irrec2 0 r/w 1 irri1 0 r/w **** note: * only a write of 0 for flag clearing is possible irr1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer a, irqaec or irq 1 , irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: timer a interrupt request flag (irrta) bit 7 irrta description 0 clearing conditions: (initial value) when irrta = 1, it is cleared by writing 0 1 setting conditions: when the timer a counter value overflows from h'ff to h'00 bits 6, 4, and 3: reserved bits bits 6, 4, and 3 are reserved; only 0 can be written to these bits. bit 5: reserved bit bit 5 is reserved; it is always read as 1 and cannot be modified.
66 bit 2: irqaec interrupt request flag (irrec2) bit 2 irrec2 description 0 clearing conditions: (initial value) when irrec2 = 1, it is cleared by writing 0 1 setting conditions: when pin irqaec is designated for interrupt input and the designated signal edge is input bits 1 and 0: irq 1 and irq 0 interrupt request flags (irri1 and irri0) bit n irrin description 0 clearing conditions: (initial value) when irrin = 1, it is cleared by writing 0 1 setting conditions: when pin irqn
67 5. interrupt request register 2 (irr2) bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 w 4 w 3 irrtfh 0 r/w 0 irrec 0 r/w 2 irrtfl 0 r/w 1 w ** ** * note: * only a write of 0 for flag clearing is possible irr2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, a/d converter, timer fh, or timer fl asynchronous event counter interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: direct transfer interrupt request flag (irrdt) bit 7 irrdt description 0 clearing conditions: (initial value) when irrdt = 1, it is cleared by writing 0 1 setting conditions: when a direct transfer is made by executing a sleep instruction while dton = 1 in syscr2 bit 6: a/d converter interrupt request flag (irrad) bit 6 irrad description 0 clearing conditions: (initial value) when irrad = 1, it is cleared by writing 0 1 setting conditions: when a/d conversion is completed and adsf is cleared to 0 in adsr bits 5 and 4: reserved bits bits 5 and 4 are reserved; only 0 can be written to these bits.
68 bit 3: timer fh interrupt request flag (irrtfh) bit 3 irrtfh description 0 clearing conditions: (initial value) when irrtfh = 1, it is cleared by writing 0 1 setting conditions: when tcfh and ocrfh match in 8-bit timer mode, or when tcf (tcfl, tcfh) and ocrf (ocrfl, ocrfh) match in 16-bit timer mode bit 2: timer fl interrupt request flag (irrtfl) bit 2 irrtfl description 0 clearing conditions: (initial value) when irrtfl= 1, it is cleared by writing 0 1 setting conditions: when tcfl and ocrfl match in 8-bit timer mode bit 1: reserved bit bit 1 is reserved; only 0 can be written to this bit. bit 0: asynchronous event counter interrupt request flag (irrec) bit 0 irrec description 0 clearing conditions: (initial value) when irrec = 1, it is cleared by writing 0 1 setting conditions: when ech overflows in 16-bit counter mode, or ech or ecl overflows in 8-bit counter mode
69 6. wakeup interrupt request register (iwpr) bit initial value read/write 7 iwpf7 0 r/w 6 iwpf6 0 r/w 5 iwpf5 0 r/w 4 iwpf4 0 r/w 3 iwpf3 0 r/w 0 iwpf0 0 r/w 2 iwpf2 0 r/w 1 iwpf1 0 r/w ** **** ** note: * only a write of 0 for flag clearing is possible iwpr is an 8-bit read/write register containing wakeup interrupt request flags. when one of pins wkp 7 to wkp 0 is designated for wakeup input and a rising or falling edge is input at that pin, the corresponding flag in iwpr is set to 1. a flag is not cleared automatically when the corresponding interrupt is accepted. flags must be cleared by writing 0. bits 7 to 0: wakeup interrupt request flags (iwpf7 to iwpf0) bit n iwpfn description 0 clearing conditions: (initial value) when iwpfn= 1, it is cleared by writing 0 1 setting conditions: when pin wkp
70 7. wakeup edge select register (wegr) bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 4 wkegs4 0 r/w 3 wkegs3 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w wegr is an 8-bit read/write register that specifies rising or falling edge sensing for pins wkp n. wegr is initialized to h'00 by a reset. bit n: wkp n edge select (wkegsn) bit n selects wkp n pin input sensing. bit n wkegsn description 0 wkp wkp 3.3.3 external interrupts there are 11 external interrupts: wkp 7 to wkp 0 , irq 1 to irq 0 , and irqaec. 1. interrupts wkp 7 to wkp 0 interrupts wkp 7 to wkp 0 are requested by either rising or falling edge input to pins wkp 7 to wkp 0 . when these pins are designated as pins wkp 7 to wkp 0 in port mode register 5 and a rising or falling edge is input, the corresponding bit in iwpr is set to 1, requesting an interrupt. recognition of wakeup interrupt requests can be disabled by clearing the ienwp bit to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when wkp 7 to wkp 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 9 is assigned to interrupts wkp 7 to wkp 0 . all eight interrupt sources have the same vector number, so the interrupt-handling routine must discriminate the interrupt source.
71 2. interrupts irq 1 and irq 0 interrupts irq 1 and irq 0 are requested by input signals to pins irq 1 and irq 0 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg1 and ieg0 in iegr. when these pins are designated as pins irq 1 and irq 0 in port mode register b and 2 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. recognition of these interrupt requests can be disabled individually by clearing bits ien1 and ien0 to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when irq 1 and irq 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector numbers 5 and 4 are assigned to interrupts irq 1 and irq 0 . the order of priority is from irq 0 (high) to irq 1 (low). table 3.2 gives details. 3. irqaec interrupt the irqaec interrupt is requested by an input signal to pin irqaec. this interrupt is detected by rising edge, falling edge, or both edge sensing, depending on the settings of bits aiags1 and aiags0 in aegsr. when bit ienec2 in ienr1 is 1 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. when irqaec interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 6 is assigned to the irqaec interrupt. table 3.2 gives details. 3.3.4 internal interrupts there are 7 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. recognition of individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2. all these interrupts can be masked by setting the i bit to 1 in ccr. when internal interrupt handling is initiated, the i bit is set to 1 in ccr. vector numbers from 20 to 18, 15, 14, 12, and 11 are assigned to these interrupts. table 3.2 shows the order of priority of interrupts from on-chip peripheral modules.
72 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3.2 shows a block diagram of the interrupt controller. figure 3.3 shows the flow up to interrupt acceptance. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals figure 3.2 block diagram of interrupt controller interrupt operation is described as follows. ? when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. ? when the interrupt controller receives an interrupt request, it sets the interrupt request flag. ? from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3.2 for a list of interrupt priorities.) ? the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending.
73 ? if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. ? the i bit of ccr is set to 1, masking further interrupts. ? the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.
74 pc contents saved ccr contents saved i figure 3.3 flow up to interrupt acceptance
75 pc and ccr saved to stack sp (r7) sp 1 sp 2 sp 3 sp 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling notation: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr pc h pc l 1. 2. * pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. ignored on return. * figure 3.4 stack state after completion of interrupt exception handling figure 3.5 shows a typical interrupt sequence.
76 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp 2 (6) sp 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.5 interrupt sequence
77 3.3.6 interrupt response time table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3.4 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 13 15 to 27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction.
78 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the h8/3802 series, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?p) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3.6. pc pc r1l pc sp sp sp h'fefc h'fefd h'feff r7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h notation: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored.
79 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. when an external interrupt pin function is switched by rewriting the port mode register that controls pins irqaec, irq 1 , irq 0 , wkp 7 to wkp 0 , the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. table 3.5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irrec2 when the edge designated by aiegs1 and aiegs0 in aegsr is input while ienec2 in ienri is set to 1. irri1 when pmrb bit irq1 is changed from 0 to 1 while pin irq irq irq irq wkp wkp wkp wkp wkp wkp wkp wkp figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared.
80 an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 figure 3.7 port mode register setting and interrupt request flag clearing procedure 3.4.3 interrupt request flag clearing method use the following recommended method for flag clearing in the interrupt request registers (irr1, irr2, and iwpr). recommended method: perform flag clearing with only one instruction. either a bit manipulation instruction or a data transfer instruction in bytes can be used. two examples of coding for clearing irri1 (bit 1 in irr1) are shown below: ? bclr #1,@irr1:8 ? mov.b r1l,@irr1:8 (set b?1111101 into r1l in advance) malfunction example : when flag clearing is performed with several instructions, a flag, other than the intended one, which was set while executing one of those instructions may be accidentally cleared, and thus cause incorrect operations to occur. an example of coding for clearing irri1 (bit 1 in irr1), in which irri0 is also cleared and the interrupt becomes invalid is shown below. mov.b @irr1:8,r1l at this point, irri0 is 0. and.b #b?1111101,r1l irri0 becomes 1 here. mov.b r1l,@irr1:8 irri0 is cleared to 0.
81 in the above example, an irq0 interrupt occurs while the and.b instruction is executed. since not only the original target irri1, but also irri0 is cleared to 0, the irq0 interrupt becomes invalid.
82
83 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x 1 2 osc (f ) osc w w (f ) w ? /2 osc ? /2 w ? /8 w sub ?2 to ?8192 ? /2 w ? /4 w ? /8 to ? /128 w w osc /128 osc /64 osc /32 osc /16 ? /4 w figure 4.1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are ?and sub . four of the clock signals have names: ?is the system clock, sub is the subclock, osc is the oscillator clock, and w is the watch clock. the clock signals available for use by peripheral modules are ?2, ?4, ?8, ?16, ?32, ?64, ?128, ?256, ?512, ?1024, ?2048, ?4096, ?8192, w , w /2, w /4, w /8, w /16, w /32, w /64, and w /128. the clock requirements differ from one module to another.
84 4.2 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. connecting a crystal oscillator figure 4.2 shows a typical method of connecting a crystal oscillator. c 1 c 2 osc 1 osc 2 r = 1 m 20% f ? r f frequency 4.19 mhz crystal oscillator ndk c 1 , c 2 recommendation value 12 pf 20% figure 4.2 typical connection to crystal oscillator figure 4.3 shows the equivalent circuit of a crystal oscillator. an oscillator having the characteristics given in table 4.1 should be used. c s c 0 r s osc 1 osc 2 l s figure 4.3 equivalent circuit of crystal oscillator table 4.1 crystal oscillator parameters frequency (mhz) 4.193 rs max ( ? ) 100 c 0 max (pf) 16
85 2. connecting a ceramic oscillator figure 4.4 shows a typical method of connecting a ceramic oscillator. 1 2 c 1 c 2 osc osc r f r = 1 m 20% f ? frequency 4.0 mhz ceramic oscillator murata c 1 , c 2 recommendation value 30 pf 10% figure 4.4 typical connection to ceramic oscillator 3. notes on board design when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4.5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 signal a signal b 2 1 to be avoided figure 4.5 board design of oscillator circuit
86 4. external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4.6 shows a typical connection. 1 2 osc osc external clock input open figure 4.6 external clock input (example) frequency oscillator clock ( osc ) duty cycle 45% to 55% note: the circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. the circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. when using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters.
87 4.3 subclock generator 1. connecting a 32.768 khz/38.4 khz crystal oscillator clock pulses can be supplied to the subclock divider by connecting a 32.768 khz/38.4 khz crystal oscillator, as shown in figure 4.7. follow the same precautions as noted under 3. notes on board design for the system clock in 4.2. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 frequency 32.768 khz 38.4 khz crystal oscillator nihon denpa kogyo seiko instrument inc. products name mx73p vtc-200 figure 4.7 typical connection to 32.768 khz/38.4 khz crystal oscillator (subclock) figure 4.8 shows the equivalent circuit of the 32.768 khz/38.4 khz crystal oscillator. c s c 0 lr s x 1 x 2 c = 1.5 pf typ r = 14 k typ f = 32.768 khz/38.4khz 0 s w ? s figure 4.8 equivalent circuit of 32.768 khz/38.4 khz crystal oscillator
88 2. pin connection when not using subclock when the subclock is not used, connect pin x 1 to gnd and leave pin x 2 open, as shown in figure 4.9. x x 1 2 gnd open figure 4.9 pin connection when not using subclock 3. external clock input connect the external clock to the x1 pin and leave the x2 pin open, as shown in figure 4.10. x 1 v cc external clock input x 2 open figure 4.10 pin connection when inputting external clock frequency subclock (?) duty 45% to 55%
89 4.4 prescalers the h8/3802 series is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock (? as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5-bit counter using a 32.768 khz or 38.4 khz signal divided by 4 ( w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. 1. prescaler s (pss) prescaler s is a 13-bit counter using the system clock (? as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by timer a, timer f, sci3, the a/d converter, the lcd controller, and the 10-bit pwm. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is ?sc/16, ?sc/32, ?sc/64, or ?sc/128. 2. prescaler w (psw) prescaler w is a 5-bit counter using a 32.768 khz/38.4 khz signal divided by 4 ( w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x1 and x2. prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping.
90 4.5 note on oscillators oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask rom and ztat versions, referring to the examples shown in this section. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. (vss) pb3 x 1 x 2 vss osc 2 osc 1 test figure 4.11 example of crystal and ceramic oscillator element arrangement 4.5.1 definition of oscillation settling standby time figure 4.12 shows the oscillation waveform (osc2), system clock (?, and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator. as shown in figure 4.12, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation settling time and standby time) is required.
91 1. oscillation settling time (t rc ) the time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. standby time the time required for the cpu and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. the standby time setting is selected with standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)). oscillation waveform (osc2) system clock ( ) oscillation settling time operating mode standby mode, watch mode, or subactive mode standby time oscillation settling standby time active (high-speed) mode or active (medium-speed) mode interrupt accepted figure 4.12 oscillation settling standby time when standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. therefore, when an oscillator element is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes?hat is, the oscillation settling time?s required.
92 the oscillation settling time in the case of these state transitions is the same as the oscillation settling time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation settling time t rc " in the ac characteristics. meanwhile, once the system clock has halted, a standby time of at least 8 states is necessary in order for the cpu and peripheral functions to operate normally. thus, the time required from interrupt generation until operation of the cpu and peripheral functions is the sum of the above described oscillation settling time and standby time. this total time is called the oscillation settling standby time, and is expressed by equation (1) below. oscillation settling standby time = oscillation settling time + standby time = t rc + (8 to 16,384 states) ................. (1) therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation settling standby time. in particular, since the oscillation settling time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the oscillator element manufacturer. 4.5.2 notes on use of crystal oscillator element (excluding ceramic oscillator element) when a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. depending on the individual crystal oscillator element characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation settling standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. in this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. if erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)) to give a longer standby time. for example, if erroneous operation occurs with a standby time setting of 16 states, check the operation with a standby time setting of 1,024 states or more. if the same kind of erroneous operation occurs after a reset as after a state transition, hold the res pin low for a longer period.
93 section 5 power-down modes 5.1 overview the h8/3802 series has nine modes of operation after a reset. these include eight power-down modes, in which power dissipation is significantly reduced. table 5.1 gives a summary of the eight operating modes. table 5.1 operating modes operating mode description active (high-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in high-speed operation active (medium-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in low-speed operation subactive mode the cpu is operable on the subclock in low-speed operation sleep (high-speed) mode the cpu halts. on-chip peripheral functions are operable on the system clock sleep (medium-speed) mode the cpu halts. on-chip peripheral functions operate at a frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency subsleep mode the cpu halts. the time-base function of timer a, timer f, sci3, aec and lcd controller/driver are operable on the subclock watch mode the cpu halts. the time-base function of timer a, timer f, aec and lcd controller/driver are operable on the subclock standby mode the cpu and all on-chip peripheral functions halt module standby mode individual on-chip peripheral functions specified by software enter standby mode and halt of these nine operating modes, all but the active (high-speed) mode are power-down modes. in this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode.
94 figure 5.1 shows the transitions among these operation modes. table 5.2 indicates the internal states in each mode. program halt state sleep instruction * e sleep instruction * c sleep instruction * h sleep instruction * i sleep instruction * g sleep instruction * f program execution state sleep instruction * a program halt state sleep instruction * i power-down modes a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is performed after the interrupt is accepted. details on the mode transition conditions are given in the explanations of each mode, in sections 5-2 through 5-8. notes: 1. 2. mode transition conditions (1) a b c d e f g h i j lson mson ssby dton 0 0 1 0 ? 0 0 0 1 0 0 1 ? ? ? 0 1 1 ? 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 * : don? care mode transition conditions (2) 1 interrupt sources timer a, timer f interrupt, irq 0 interrupt, wkp 7 to wkp 0 interrupts timer a, timer f, sci3 interrupt, irq 1 and irq 0 interrupts, irqaec, wkp 7 to wkp 0 interrupts, aec all interrupts irq 1 or irq 0 interrupt, wkp 7 to wkp 0 interrupts 2 3 4 * 3 * 3 * 2 * 1 * 4 * 4 * 1 standby mode watch mode subactive mode active (medium-speed) mode active (high-speed) mode sleep (high-speed) mode sleep (medium-speed) mode subsleep mode sleep instruction * a sleep instruction * e sleep instruction * d sleep instruction * b sleep instruction * j * 1 sleep instruction * e sleep instruction * b tma3 ? ? 1 0 1 ? ? 1 1 1 sleep instruction * d reset state figure 5.1 mode transition diagram
95 table 5.2 internal state in each operating mode active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subactive mode subsleep mode standby mode system clock oscillator functions functions functions functions halted halted halted halted subclock oscillator functions functions functions functions functions functions functions functions cpu instructions functions functions halted halted halted functions halted halted operations ram retained retained retained retained retained registers i/o ports retained * 1 external irq 0 functions functions functions functions functions functions functions functions interrupts irq 1 retained * 5 irqaec retained * 5 wkp 0 functions functions functions functions functions functions functions functions wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 peripheral timer a functions functions functions functions functions * 4 functions * 4 functions * 4 retained functions asynchronous counter functions * 6 functions functions functions * 6 timer f functions/ retained * 7 functions/ retained * 7 functions/ retained * 7 retained sci3 reset functions/ retained * 2 functions/ retained * 2 reset pwm retained retained retained retained a/d converter retained retained retained retained lcd functions/ retained * 3 functions/ retained * 3 functions/ retained * 3 retained notes: 1. register contents are retained, but output is high-impedance state. 2. functions if w /2 is selected as the internal clock; otherwise halted and retained. 3. functions if w , w /2 or w /4 is selected as the operating clock; otherwise halted and retained. 4. functions if the timekeeping time-base function is selected. 5. external interrupt requests are ignored. interrupt request register contents are not altered. 6. incrementing is possible, but interrupt generation is not. 7. functions if the w /4 internal clock is selected; otherwise halted and retained.
96 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5.3. table 5.3 system control registers name abbreviation r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'f0 h'fff1 1. system control register 1 (syscr1) b it i nitial value r ead/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 1 1 ma1 1 r/w syscr1 is an 8-bit read/write register for control of the power-down modes. upon reset, syscr1 is initialized to h'07. bit 7: software standby (ssby) this bit designates transition to standby mode or watch mode. bit 7 ssby description 0 ? ? ? ?
97 bits 6 to 4: standby timer select 2 to 0 (sts2 to sts0) these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 wait time = 8,192 states (initial value) 0 0 1 wait time = 16,384 states 0 1 0 wait time = 1,024 states 0 1 1 wait time = 2,048 states 1 0 0 wait time = 4,096 states 1 0 1 wait time = 2 states (external clock mode) 1 1 0 wait time = 8 states 1 1 1 wait time = 16 states note: in the case that external clock is input, set up the standby timer select selection to external clock mode before mode transition. also, do not set up to external clock mode, in the case that it does not use external clock. bit 3: low speed on flag (lson) this bit chooses the system clock (? or subclock ( sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3 lson description 0 the cpu operates on the system clock ( ) (initial value) 1 the cpu operates on the subclock ( sub) bits 2: reserved bit bit 2 is reserved: it is always read as 1 and cannot be modified.
98 bits 1 and 0: active (medium-speed) mode clock select (ma1, ma0) bits 1 and 0 choose osc /128, osc /64, osc /32, or osc /16 as the operating clock in active (medium- speed) mode and sleep (medium-speed) mode. ma1 and ma0 should be written in active (high- speed) mode or subactive mode. bit 1 ma1 bit 0 ma0 description 00 osc /16 01 osc /32 10 osc /64 11 osc /128 (initial value) 2. system control register 2 (syscr2) b it i nitial value r ead/write 7 1 6 1 5 1 4 nesel 1 r/w 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w syscr2 is an 8-bit read/write register for power-down mode control. bits 7 to 5: reserved bits these bits are reserved; they are always read as 1, and cannot be modified. bit 4: noise elimination sampling frequency select (nesel) this bit selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc = 2 to 16 mhz, clear nesel to 0. bit 4 nesel description 0 sampling rate is osc /16 1 sampling rate is osc /4 (initial value)
99 bit 3: direct transfer on flag (dton) this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of this and other control bits. bit 3 dton description 0 ? ? ? ? ? bit 2: medium speed on flag (mson) after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2 mson description 0 operation in active (high-speed) mode (initial value) 1 operation in active (medium-speed) mode
100 bits 1 and 0: subactive mode clock select (sa1 and sa0) these bits select the cpu clock rate ( w /2, w /4, or w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1 sa1 bit 0 sa0 description 00 w /8 (initial value) 01 w /4 1 * w /2 * : don t care
101 5.2 sleep mode 5.2.1 transition to sleep mode 1. transition to sleep (high-speed) mode the system goes from active mode to sleep (high-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson and dton bits in syscr2 are cleared to 0. in sleep mode cpu operation is halted but the on-chip peripheral functions. cpu register contents are retained. 2. transition to sleep (medium-speed) mode the system goes from active mode to sleep (medium-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is cleared to 0. in sleep (medium-speed) mode, as in sleep (high-speed) mode, cpu operation is halted but the on-chip peripheral functions are operational. the clock frequency in sleep (medium-speed) mode is determined by the ma1 and ma0 bits in syscr1. cpu register contents are retained. furthermore, it sometimes acts with half state early timing at the time of transition to sleep (medium-speed) mode. 5.2.2 clearing sleep mode sleep mode is cleared by any interrupt (timer a, timer f, asynchronous counter, irqaec, irq 1 , irq 0 , wkp 7 to wkp 0 , sci3, a/d converter), or by input at the res pin. ? clearing by interrupt when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. a transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. interrupt signal and system clock are mutually asynchronous. synchronization error time in a maximum is 2/?(s). ? clearing by res input when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared.
102 5.2.3 clock frequency in sleep (medium-speed) mode operation in sleep (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1. 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of cpu registers, on-chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be further retained down to a minimum ram data retention voltage. the i/o ports go to the high-impedance state. 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 1 or irq 0 ), wkp 7 to wkp 0 or by input at the res pin. ? clearing by interrupt when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input when the res pin goes low, the system clock pulse generator starts. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes.
103 5.3.3 oscillator settling time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. ? when a crystal oscillator is used the table below gives settings for various operating frequencies. set bits sts2 to sts0 for a waiting time at least as long as the oscillation settling time. table 5.4 clock frequency and settling time (times are in ms) sts2 sts1 sts0 waiting time 5 mhz 2 mhz 0 0 0 8,192 states 1.638 4.1 0 0 1 16,384 states 3.277 8.2 0 1 0 1,024 states 0.205 0.512 0 1 1 2,048 states 0.410 1.024 1 0 0 4,096 states 0.819 2.048 1012 states (use prohibited) 0.0004 0.001 1108 states 0.0002 0.004 1 1 1 16 states 0.003 0.008 ? when an external clock is used sts2 = 1, sts1 = 0, and sts0 = 1 should be set. other values possible use, but cpu sometimes will start operation before waiting time completion.
104 5.3.4 standby mode transition and pin states when a sleep instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, and bit tma3 is cleared to 0 in tma, a transition is made to standby mode. at the same time, pins go to the high- impedance state (except pins for which the pull-up mos is designated as on). figure 5.2 shows the timing in this case. sleep instruction fetch internal data bus fetch of next instruction port output pins high-impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 standby mode transition and pin states
105 5.3.5 notes on external input signal changes before/after standby mode 1. when external input signal changes before/after standby mode or watch mode when an external input signal such as irq , wkp , or irqaec is input, both the high- and low-level widths of the signal must be at least two cycles of system clock ?or subclock sub (referred to together in this section as the internal clock). as the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. ensure that external input signals conform to the conditions stated in 3, recommended timing of external input signals, below 2. when external input signals cannot be captured because internal clock stops the case of falling edge capture is illustrated in figure 5.3 as shown in the case marked "capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 t cyc or 2 t subcyc . 3. recommended timing of external input signals to ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 t cyc or 2 t subcyc are necessary before a transition is made to standby mode or watch mode, as shown in "capture possible: case 1." external input signal capture is also possible with the timing shown in "capture possible: case 2" and "capture possible: case 3," in which a 2 t cyc or 2 t subcyc level width is secured.
106 t cyc t subcyc operating mode or sub capture possible: case 1 capture possible: case 2 capture possible: case 3 capture not possible interrupt by different signall external input signal active (high-speed, medium-speed) mode or subactive mode active (high-speed, medium-speed) mode or subactive mode standby mode or watch mode wait for oscillation to settle t cyc t subcyc t cyc t subcyc t cyc t subcyc figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode 4. input pins to which these notes apply: irq 1 to irq 0 , wkp 7 to wkp 0 , irqaec
107 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules is halted except for timer a, timer f, aec and the lcd controller/driver (for which operation or halting can be set) is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules, are retained. i/o ports keep the same states as before the transition. 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, timer f, irq 0 , or wkp 7 to wkp 0 ) or by input at the res pin. ? clearing by interrupt when watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2 to sts0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input clearing by res pin is the same as for standby mode; see 2. clearing by res pin in 5.3.2, clearing standby mode. 5.4.3 oscillator settling time after watch mode is cleared the waiting time is the same as for standby mode; see 5.3.3, oscillator settling time after standby mode is cleared. 5.4.4 notes on external input signal changes before/after watch mode see 5.3.5, notes on external input signal changes before/after standby mode.
108 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson bit in syscr1 is set to 1, and tma3 bit in tma is set to 1. in subsleep mode, operation of on-chip peripheral modules other than the a/d converter, and pwm is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer f, asynchronous counter, sci3, irqaec, irq 1 , irq 0 , wkp 7 to wkp 0 ) or by a low input at the res pin. ? clearing by interrupt when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. interrupt signal and system clock are mutually asynchronous. synchronization error time in a maximum is 2/ sub (s). ? clearing by res input clearing by res pin is the same as for standby mode; see clearing by res pin in 5.3.2, clearing standby mode.
109 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, timer f, irq 0 , or wkp 7 to wkp 0 interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer f, asynchronous event counter, sci3, irqaec, irq 1 , irq 0 , or wkp 7 to wkp 0 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a low input at the res pin. ? clearing by sleep instruction if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see 5.8, direct transfer, below. ? clearing by res pin clearing by res pin is the same as for standby mode; see clearing by res pin in 5.3.2, clearing standby mode. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are w /2, w /4, and w /8.
110 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the res pin is driven low, active (medium-speed) mode is entered. if the lson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 or wkp 7 to wkp 0 interrupts in standby mode, timer a, timer f, irq 0 , or wkp 7 to wkp 0 interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. furthermore, it sometimes acts with half state early timing at the time of transition to active (medium-speed) mode. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction. ? clearing by sleep instruction a transition to standby mode takes place if the sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and the tma3 bit in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1 when a sleep instruction is executed. when both ssby and lson are cleared to 0 in syscr1 and a sleep instruction is executed, sleep mode is entered. direct transfer to active (high-speed) mode or to subactive mode is also possible. see 5.8, direct transfer, below for details. ? clearing by res pin when the res pin is driven low, a transition is made to the reset state and active (medium-speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode operation in active (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1.
111 5.8 direct transfer 5.8.1 overview of direct transfer the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. if the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. ? direct transfer from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. ? direct transfer from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. ? direct transfer from active (high-speed) mode to subactive mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed.
112 ? direct transfer from active (medium-speed) mode to subactive mode when a sleep instruction is executed in active (medium-speed) while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 5.8.2 direct transition times 1. time for direct transition from active (high-speed) mode to active (medium-speed) mode a direct transition from active (high-speed) mode to active (medium-speed) mode is performed by executing a sleep instruction in active (high-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bits mson and dton are both set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (1) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (1) example: direct transition time = (2 + 1) 2tosc + 14 16tosc = 230tosc (when ?8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock (? cycle time
113 2. time for direct transition from active (medium-speed) mode to active (high-speed) mode a direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a sleep instruction in active (medium-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bit mson is cleared to 0 and bit dton is set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (2) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (2) example: direct transition time = (2 + 1) 16tosc + 14 2tosc = 76tosc (when ?8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock (? cycle time 3. time for direct transition from subactive mode to active (high-speed) mode a direct transition from subactive mode to active (high-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bit mson is cleared to 0 and bit dton is set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (3) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (3) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 2tosc = 24tw + 16412tosc (when ?/8 is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock (? cycle time tsubcyc: subclock (?ub) cycle time
114 4. time for direct transition from subactive mode to active (medium-speed) mode a direct transition from subactive mode to active (medium-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bits mson and dton are both set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (4) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (4) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 16tosc = 24tw + 131296tosc (when ?/8 or ? is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock (? cycle time tsubcyc: subclock (?ub) cycle time 5.8.3 notes on external input signal changes before/after direct transition 1. direct transition from active (high-speed) mode to subactive mode since the mode transition is performed via watch mode, see 5.3.5, notes on external input signal changes before/after standby mode. 2. direct transition from active (medium-speed) mode to subactive mode since the mode transition is performed via watch mode, see 5.3.5, notes on external input signal changes before/after standby mode. 3. direct transition from subactive mode to active (high-speed) mode since the mode transition is performed via watch mode, see 5.3.5, notes on external input signal changes before/after standby mode. 4. direct transition from subactive mode to active (medium-speed) mode since the mode transition is performed via watch mode, see 5.3.5, notes on external input signal changes before/after standby mode.
115 5.9 module standby mode 5.9.1 setting module standby mode module standby mode is set for individual peripheral functions. all the on-chip peripheral modules can be placed in module standby mode. when a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. this state is identical to standby mode. module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) 5.9.2 clearing module standby mode module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) following a reset, clock stop register 1 (ckstpr1) and clock stop register 2 (ckstpr2) are both initialized to h'ff. table 5.5 register name bit name operation ckstpr1 tackstp 1 timer a module standby mode is cleared 0 timer a is set to module standby mode tfckstp 1 timer f module standby mode is cleared 0 timer f is set to module standby mode adckstp 1 a/d converter module standby mode is cleared 0 a/d converter is set to module standby mode s32ckstp 1 sci3 module standby mode is cleared 0 sci3 is set to module standby mode
116 register name bit name operation ckstpr2 ldckstp 1 lcd module standby mode is cleared 0 lcd is set to module standby mode pw1ckstp 1 pwm1 module standby mode is cleared 0 pwm1 is set to module standby mode aeckstp 1 asynchronous event counter module standby mode is cleared 0 asynchronous event counter is set to module standby mode pw2ckstp 1 pwm2 module standby mode is cleared 0 pwm2 is set to module standby mode note: for details of module operation, see the sections on the individual modules.
117 section 6 rom 6.1 overview the h8/3802 has 16 kbytes of on-chip mask rom, the h8/3801 has 12 kbytes, and the h8/3800 has 8 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two- state access for both byte data and word data. the h8/3802 has a ztat version with 16-kbyte prom. 6.1.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. h'3ffe h'3fff internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'3ffe h'0002 h'0000 h'0000 h'0002 h'0001 h'0003 on-chip rom figure 6.1 rom block diagram (h8/3802)
118 6.2 h8/3802 prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c101 eprom. however, page programming is not supported. table 6.1 shows how to set the chip to prom mode. table 6.1 setting to prom mode pin name setting test high level pb 0 /an 0 low level pb 1 /an 1 pb 2 /an 2 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map.
119 hn27c101 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ce oe pgm v cc v ss note: pins not indicated in the figure should be left open. eprom socket fp-64a, fp-64e dp-64s pin 8 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 60 30 29 28 27 26 52 53 25 31 51 16 61 7 2 64 49 50 54 55 4 62 63 16 48 47 46 45 44 43 42 41 1 2 18 19 20 21 22 23 40 4 38 37 36 35 34 60 61 33 39 59 24 5 15 10 8 57 58 62 63 12 6 7 res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p4 0 p4 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 p7 0 p4 3 p7 2 p7 3 p7 4 p7 5 p7 6 p9 3 p9 4 p7 7 p7 1 p9 2 v cc av cc test x 1 pb 2 p9 0 p9 1 p9 5 v ss av ss pb 0 pb 1 h8/3802 figure 6.2 socket adapter pin correspondence (with hn27c101)
120 address in mcu mode address in prom mode h'0000 h'0000 h'1ffff h'3fff h'3fff on-chip prom uninstalled area * the output data is not guaranteed if this address area is read in prom mode. there- fore, when programming with a prom programmer, be sure to specify addresses from h'0000 to h'3fff. if programming is inadvertently performed from h'4000 on- ward, it may not be possible to continue prom programming and verification. when programming, h'ff should be set as the data in this address area (h'4000 to h'1ffff). note: * figure 6.3 h8/3802 memory map in prom mode
121 6.3 h8/3802 programming the write, verify, and other modes are selected as shown in table 6.2 in h8/3802 prom mode. table 6.2 mode selection in prom mode (h8/3802) pins mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming l l l v pp v cc high impedance address input disabled l h h hl l hhh notation l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading are identical to those for the standard hn27c101 eprom. however, page programming is not supported, and so page programming mode must not be set. a prom programmer that only supports page programming mode cannot be used. when selecting a prom programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. also, be sure to specify addresses from h'0000 to h'3fff. 6.3.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6.4.
122 start set write/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n pw verify write time t opw = 0.2n ms last address? set read mode v = 5.0 v 0.25 v, v = v cc pp cc read all addresses? end error n 25 < address + 1 address no yes no go go yes no no go go write time t = 0.2 ms 5% figure 6.4 high-speed, high-reliability programming flow chart
123 table 6.3 and table 6.4 give the electrical characteristics in programming mode. table 6.3 dc characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25 c ? c) item symbol min typ max unit test condition input high- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v ih 2.4 v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v il ?.3 0.8 v output high- level voltage eo 7 to eo 0 v oh 2.4 v i oh = ?00 ? output low- level voltage eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm |i li | 2 ? v in = 5.25 v/ 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma
124 table 6.4 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25 c ? c) item symbol min typ max unit test condition address setup time t as 2 s figure 6.5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 5.25 ms ce setup time t ces 2 s v cc setup time t vcs 2 s data output delay time t oe 0 200 ns notes: 1. input pulse level: 0.45 v to 2.2 v input rise time/fall time 20 ns timing reference levels input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6.4, high-speed, high-reliability programming flow chart.
125 figure 6.5 shows a prom write/verify timing diagram. write input data output data verify address data v pp v pp t as t ah t ds t dh t df t oe t oes t pw t opw * t vps t vcs t ces v cc v cc ce pgm oe v cc +1 v cc note: * t opw is defined by the value shown in figure 6.4, high-speed, high-reliability programming flowchart. figure 6.5 prom write/verify timing
126 6.3.2 programming precautions ? ? ? ? ?
127 6.4 reliability of programmed data a highly effective way to improve data retention characteristics is to bake the programmed chips at 150 c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 6.6 shows the recommended screening procedure. program chip and verify programmed data bake chip for 24 to 48 hours at 125 figure 6.6 recommended screening procedure if a series of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
128
129 section 7 ram 7.1 overview the h8/3802 has 1 kbyte of high-speed static ram on-chip, and the h8/3801 and h8/3800 have 512 bytes. the ram is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. h'ff7e h'ff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'ff7e h'fb82 h'fb80 h'fb80 h'fb82 h'fb81 h'fb83 on-chip ram figure 7.1 ram block diagram (h8/3802)
130
131 section 8 i/o ports 8.1 overview the h8/3802 series is provided with three 8-bit i/o ports, one 7-bit i/o port, one 4-bit i/o port, one 3-bit i/o port, one 1-bit i/o port, one 4-bit input-only port, one 1-bit input-only port, and one 6-bit output-only port. table 8.1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. see 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. ports 5, 6, 7, 8, and a are also used as liquid crystal display segment and common pins, selectable in 4-bit units. block diagrams of each port are given in appendix c, i/o port block diagrams. table 8.1 port functions port description pins other functions function switching registers port 3 ? 7-bit i/o port ? mos input pull-up option ? large-current port p3 7 /aevl p3 6 /aevh p3 5, p3 4, p3 3 asynchronous event counter event inputs aevl, aevh pmr3 p3 2 , tmofh p3 1 , tmofl timer f output compare output pmr3 port 4 ? 1-bit input port p4 3 / irq 0 external interrupt 0 pmr2 ? 3-bit i/o port p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 sci3 data output (txd 32 ), data input (rxd 32 ), clock input/output (sck 32 ) scr3 smr port 5 ? 8-bit i/o port ? mos input pull-up option p5 7 to p5 0 / wkp 7 to wkp 0 / seg 8 to seg 1 wakeup input ( wkp 7 to wkp 0 ), segment output (seg 8 to seg 1 ) pmr5 lpcr
132 port description pins other functions function switching registers port 6 ? 8-bit i/o port ? mos input pull-up option p6 7 to p6 0 / seg 16 to seg 9 segment output (seg 16 to seg 9 ) lpcr port 7 ? 8-bit i/o port p7 7 to p7 0 / seg 24 to seg 17 segment output (seg 24 to seg 17 ) lpcr port 8 ? 1-bit i/o port p8 0 /seg 25 , segment output lpcr port 9 ? 6-bit output port p9 5 to p9 2 none ? high-voltage, large- current port p9 1 , p9 0 / pwm2, pwm1 10-bit pwm output pmr9 ? high-voltage port irqaec none port a 4-bit i/o port pa 3 to pa 0 / com 4 to com 1 common output (com 4 to com 1 ) lpcr port b 4-bit input port pb 3 to pb 0 / an 3 to an 0 a/d converter analog input amr
133 8.2 port 3 8.2.1 overview port 3 is a 7-bit i/o port, configured as shown in figure 8.1. p3 /aevl p3 /aevh p3 7 6 5 port 3 p3 p3 p3 /tmofh 4 3 2 p3 /tmofl 1 figure 8.1 port 3 pin configuration 8.2.2 register configuration and description table 8.2 shows the port 3 register configuration. table 8.2 port 3 registers name abbrev. r/w initial value address port data register 3 pdr3 r/w h'ffd6 port control register 3 pcr3 w h'ffe6 port pull-up control register 3 pucr3 r/w h'ffe1 port mode register 3 pmr3 r/w h'ffca port mode register 2 pmr2 r/w h'ffc9
134 1. port data register 3 (pdr3) bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 2 p3 0 r/w 1 p3 0 r/w 21 54 76 3 pdr3 is an 8-bit register that stores data for port 3 pins p3 7 to p3 1 . if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. 2. port control register 3 (pcr3) bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 w 2 pcr3 0 w 1 pcr3 0 w 21 54 3 76 pcr3 is an 8-bit register for controlling whether each of the port 3 pins p3 7 to p3 1 functions as an input pin or output pin. setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. pcr3 is a write-only register. bits 7 to 1 are always read as 1. bit 0 is reserved; only 0 can be written to this bit. 3. port pull-up control register 3 (pucr3) bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 w 2 pucr3 0 r/w 1 pucr3 0 r/w 2 1 5 43 76 pucr3 controls whether the mos pull-up of each of the port 3 pins p3 7 to p3 1 is on or off. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. bit 0 is reserved; only 0 can be written to this bit.
135 4. port mode register 3 (pmr3) b it i nitial value r ead/write 7 aevl 0 r/w 6 aevh 0 r/w 5 w 4 w 3 w 0 w 2 tmofh 0 r/w 1 tmofl 0 r/w pmr3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. bit 7: p3 7 /aevl pin function switch (aevl) this bit selects whether pin p3 7 /aevl is used as p3 7 or as aevl. bit 7 aevl description 0 functions as p3 7 i/o pin (initial value) 1 functions as aevl input pin bit 6: p3 6 /aevh pin function switch (aevh) this bit selects whether pin p3 6 /aevh is used as p3 6 or as aevh. bit 6 aevh description 0 functions as p3 6 i/o pin (initial value) 1 functions as aevh input pin bits 5 to 3: reserved bits bits 5 to 3 are reserved; only 0 can be written to these bits. bit 2: p3 2 /tmofh pin function switch (tmofh) this bit selects whether pin p3 2 /tmofh is used as p3 2 or as tmofh. bit 2 tmofh description 0 functions as p3 2 i/o pin 1 functions as tmofh output pin (initial value)
136 bit 1: p3 1 /tmofl pin function switch (tmofl) this bit selects whether pin p3 1 /tmofl is used as p3 1 or as tmofl. bit 1 tmofl description 0 functions as p3 1 i/o pin (initial value) 1 functions as tmofl output pin bit 0: reserved bit bit 0 is reserved; only 0 can be written to this bit. 5. port mode register 2 (pmr2) bit initial value read/write 7 1 6 1 5 pof1 0 r/w 4 1 3 1 0 irq 0 0 r/w 2 w 1 w pmr2 is an 8-bit read/write register controlling the pmos on/off state for the p3 5 pin. bit 5: p3 5 pin pmos control (pof1) this bit controls the on/off state of the p3 5 pin output buffer pmos. bit 5 pof1 description 0 cmos output (initial value) 1 nmos open-drain output
137 8.2.3 pin functions table 8.3 shows the port 3 pin functions. table 8.3 port 3 pin functions pin pin functions and selection method p3 7 /aevl the pin function depends on bit aevl in pmr3 and bit pcr3 2 in pcr3. aevl 0 1 pcr3 7 01 * pin function p3 7 input pin p3 7 output pin aevl input pin p3 6 /aevh the pin function depends on bit aevh in pmr3 and bit pcr3 6 in pcr3. aevh 0 1 pcr3 6 01 * pin function p3 6 input pin p3 6 output pin aevh input pin p3 5 to p3 3 the pin function depends on the corresponding bit in pcr3. pcr3n 0 1 pin function p3 n input pin p3 n output pin (n = 5 to 3) p3 2 /tmofh the pin function depends on bit tmofh in pmr3 and bit pcr3 2 in pcr3. tmofh 0 1 pcr3 2 01 * pin function p3 2 input pin p3 2 output pin tmofh output pin p3 1 /tmofl the pin function depends on bit tmofl in pmr3 and bit pcr3 1 in pcr3. tmofl 0 1 pcr3 1 01 * pin function p3 1 input pin p3 1 output pin thofl output pin * : don t care
138 8.2.4 pin states table 8.4 shows the port 3 pin states in each operating mode. table 8.4 port 3 pin states pins reset sleep subsleep standby watch subactive active p3 7 /aevl p3 6 /aevh p3 5 p3 4 p3 3 p3 2 /tmofh p3 1 /tmofl high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.2.5 mos input pull-up port 3 has a built-in mos input pull-up function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr3 n 00 1 pucr3 n 01 * mos input pull-up off on off (n = 7 to 1) * : don t care
139 8.3 port 4 8.3.1 overview port 4 is a 3-bit i/o port and 1-bit input port, configured as shown in figure 8.2. p4 p4 p4 p4 / irq figure 8.2 port 4 pin configuration 8.3.2 register configuration and description table 8.5 shows the port 4 register configuration. table 8.5 port 4 registers name abbrev. r/w initial value address port data register 4 pdr4 r/w h'f8 h'ffd7 port control register 4 pcr4 w h'f8 h'ffe7 port mode register 2 pmr2 r/w h'ffc9 1. port data register 4 (pdr4) b it i nitial value r ead/write 7 1 6 1 5 1 4 1 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 3210 pdr4 is an 8-bit register that stores data for port 4 pins p4 2 to p4 0 . if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read. upon reset, pdr4 is initialized to h'f8.
140 2. port control register 4 (pcr4) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w 210 pcr4 is an 8-bit register for controlling whether each of port 4 pins p4 2 to p4 0 functions as an input pin or output pin. setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr4 and pdr4 settings are valid when the corresponding pins are designated for general-purpose input/output by scr3-2. upon reset, pcr4 is initialized to h'f8. pcr4 is a write-only register, which is always read as all 1s. 3. port mode register 2 (pmr2) bit initial value read/write 7 1 6 1 5 pof1 0 r/w 4 1 3 1 0 irq 0 0 r/w 2 w 1 w pmr2 is an 8-bit read/write register controlling the selection of the p4 3 /irq 0 pin function and the pmos on/off state for the p3 5 pin. upon reset, pmr2 is initialized to h'de. bits 7, 6, 4, and 3: reserved bits bits 7, 6, and 4 to 1 are reserved; they are always read as 1 and cannot be modified. bit 5: p3 5 pin pmos control (pof1) this bit controls the on/off state of the p3 5 pin output buffer pmos. bit 5 pof1 description 0 cmos output (initial value) 1 nmos open-drain output bits 2 and 1: reserved bits bits 2 and 1 are reserved; only 0 can be written to these bits.
141 bit 0: p4 3 /irq 0 pin function switch (irq 0 ) this bit selects whether pin p4 3 / irq 0 is used as p4 3 or as irq 0 . bit 0 irq 0 description 0 functions as p4 3 input pin (initial value) 1 functions as irq 8.3.3 pin functions table 8.6 shows the port 4 pin functions. table 8.6 port 4 pin functions pin pin functions and selection method p4 3 / irq irq * pin function p4 2 input pin p4 2 output pin txd 32 output pin p4 1 /rxd 32 the pin function depends on bit re in scr3 and bit pcr4 1 in pcr4. re 0 1 pcr4 1 01 * pin function p4 1 input pin p4 1 output pin rxd 32 input pin
142 pin pin functions and selection method p4 0 /sck 32 the pin function depends on bit cke1 and cke0 in scr3, bit com in smr, and bit pcr4 0 in pcr4. cke1 0 1 cke0 0 1 * com 0 1 ** pcr4 0 01 ** pin function p4 0 input pin p4 0 output pin sck 32 output pin sck 32 input pin * : don t care 8.3.4 pin states table 8.7 shows the port 4 pin states in each operating mode. table 8.7 port 4 pin states pins reset sleep subsleep standby watch subactive active p4 3 /irq 0 p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
143 8.4 port 5 8.4.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8.3. p5 7 / wkp wkp wkp wkp wkp wkp wkp wkp figure 8.3 port 5 pin configuration 8.4.2 register configuration and description table 8.8 shows the port 5 register configuration. table 8.8 port 5 registers name abbrev. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ffe2 port mode register 5 pmr5 r/w h'00 h'ffcc
144 1. port data register 5 (pdr5) bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 76543210 pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. 2. port control register 5 (pcr5) bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w 76543210 pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr5 and pdr5 settings are valid when the corresponding pins are designated for general-purpose input/output by pmr5 and bits sgs3 to sgs0 in lpcr. upon reset, pcr5 is initialized to h'00. pcr5 is a write-only register, which is always read as all 1s. 3. port pull-up control register 5 (pucr5) bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 76543210 pucr5 controls whether the mos pull-up of each of port 5 pins p5 7 to p5 0 is on or off. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00.
145 4. port mode register 5 (pmr5) b it i nitial value r ead/write 7 wkp 7 0 r/w 6 wkp 6 0 r/w 5 wkp 5 0 r/w 4 wkp 4 0 r/w 3 wkp 3 0 r/w 0 wkp 0 0 r/w 2 wkp 2 0 r/w 1 wkp 1 0 r/w pmr5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. upon reset, pmr5 is initialized to h'00. bit n: p5 n / wkp n /seg n+1 pin function switch (wkpn) when pin p5n/ wkp n/segn+1 is not used as seg n+1 , these bits select whether the pin is used as p5n or wkp n . bit n wkpn description 0 functions as p5n i/o pin (initial value) 1 functions as wkp
146 8.4.3 pin functions table 8.9 shows the port 5 pin functions. table 8.9 port 5 pin functions pin pin functions and selection method p5 7 / wkp wkp * pcr5 n 01 ** pin function p5 n input pin p5 n output pin wkpn * pcr5 m 01 ** pin function p5 m input pin p5 m output pin wkpm * : don t care
147 8.4.4 pin states table 8.10 shows the port 5 pin states in each operating mode. table 8.10 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 / wkp wkp * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.4.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 00 1 pucr5 n 01 * mos input pull-up off on off (n = 7 to 0) * : don t care
148 8.5 port 6 8.5.1 overview port 6 is an 8-bit i/o port. the port 6 pin configuration is shown in figure 8.4. p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 port 6 figure 8.4 port 6 pin configuration 8.5.2 register configuration and description table 8.11 shows the port 6 register configuration. table 8.11 port 6 registers name abbrev. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 port pull-up control register 6 pucr6 r/w h'00 h'ffe3
149 1. port data register 6 (pdr6) b it i nitial value r ead/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 210 54 76 3 pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. upon reset, pdr6 is initialized to h'00. 2. port control register 6 (pcr6) bit initial value read/write 7 pcr6 7 0 w 6 pcr6 6 0 w 5 pcr6 5 0 w 4 pcr6 4 0 w 3 pcr6 3 0 w 0 pcr6 0 0 w 2 pcr6 2 0 w 1 pcr6 1 0 w pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. setting a pcr6 bit to 1 makes the corresponding pin (p6 7 to p6 0 ) an output pin, while clearing the bit to 0 makes the pin an input pin. pcr6 and pdr6 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr6 is initialized to h'00. pcr6 is a write-only register, which is always read as all 1s.
150 3. port pull-up control register 6 (pucr6) bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 2 10 5 43 76 pucr6 controls whether the mos pull-up of each of the port 6 pins p6 7 to p6 0 is on or off. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr6 is initialized to h'00. 8.5.3 pin functions table 8.12 shows the port 6 pin functions. table 8.12 port 6 pin functions pin pin functions and selection method p6 7 /seg 16 to p6 0 /seg 9 the pin function depends on bit pcr6n in pcr6 and bits sgs3 to sgs0 in lpcr. p6 7 to p6 4 (n = 7 to 4) seg3 to segs0 other than 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011 pcr6 n 01 * pin function p6 n input pin p6 n output pin seg n+9 output pin p6 3 to p6 0 (m = 3 to 0) seg3 to segs0 other than 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010 pcr6 m 01 * pin function p6 m input pin p6 m output pin seg n+9 output pin * : don t care
151 8.5.4 pin states table 8.13 shows the port 6 pin states in each operating mode. table 8.13 port 6 pin states pin reset sleep subsleep standby watch subactive active p6 7 /seg 16 to p6 0 /seg 9 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.5.5 mos input pull-up port 6 has a built-in mos pull-up function that can be controlled by software. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr6 n 00 1 pucr6 n 01 * mos input pull-up off on off (n = 7 to 0) * : don t care
152 8.6 port 7 8.6.1 overview port 7 is an 8-bit i/o port, configured as shown in figure 8.5. p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 port 7 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 figure 8.5 port 7 pin configuration 8.6.2 register configuration and description table 8.14 shows the port 7 register configuration. table 8.14 port 7 registers name abbrev. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea
153 1. port data register 7 (pdr7) b it i nitial value r ead/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 76543210 pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. upon reset, pdr7 is initialized to h'00. 2. port control register 7 (pcr7) b it i nitial value r ead/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w 76543210 pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr7 and pdr7 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register, which is always read as all 1s.
154 8.6.3 pin functions table 8.15 shows the port 7 pin functions. table 8.15 port 7 pin functions pin pin functions and selection method p7 7 /seg 24 to p7 0 /seg 17 the pin function depends on bit pcr7 n in pcr7 and bits sgs3 to sgs0 in lpcr. p7 7 to p7 4 (n = 7 to 4) segs3 to segs0 other than 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101 pcr7 n 01 * pin function p7 n input pin p7 n output pin seg n+17 output pin p7 3 to p7 0 (m = 3 to 0) segs3 to segs0 other than 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 pcr7 m 01 * pin function p7 m input pin p7 m output pin seg m+17 output pin * : don t care 8.6.4 pin states table 8.16 shows the port 7 pin states in each operating mode. table 8.16 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 /seg 24 to p7 0 /seg 17 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
155 8.7 port 8 8.7.1 overview port 8 is an 1-bit i/o port configured as shown in figure 8.6. port 8 p8 0 /seg 25 figure 8.6 port 8 pin configuration 8.7.2 register configuration and description table 8.17 shows the port 8 register configuration. table 8.17 port 8 registers name abbrev. r/w initial value address port data register 8 pdr8 r/w h'ffdb port control register 8 pcr8 w h'ffeb
156 1. port data register 8 (pdr8) bit initial value read/write 7 6 5 4 3 0 p8 0 r/w 2 1 0 pdr8 is an 8-bit register that stores data for port 8 pin p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. 2. port control register 8 (pcr8) bit initial value read/write 7 w 6 w 5 w 4 w 3 w 0 pcr8 0 w 2 w 1 w pcr8 is an 8-bit register for controlling whether the port 8 pin p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr8 and pdr8 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. pcr8 is a write-only register, which is always read as all 1s. bits 7 to 1: reserved bits bits 7 to 1 are reserved; only 0 can be written to these bits.
157 8.7.3 pin functions table 8.18 shows the port 8 pin functions. table 8.18 port 8 pin functions pin pin functions and selection method p8 0 /seg 25 the pin function depends on bit pcr8 n in pcr8 and bits sgs3 to sgs0 in lpcr. segs3 to segs0 other than 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 pcr8 0 01 * pin function p8 0 input pin p8 0 output pin seg 25 output pin * : don t care 8.7.4 pin states table 8.19 shows the port 8 pin states in each operating mode. table 8.19 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 0 /seg 25 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
158 8.8 port 9 8.8.1 overview port 9 is a 6-bit output-only port, configured as shown in figure 8.7. p9 5 p9 4 p9 3 p9 2 p9 1 /pwm 2 p9 0 /pwm 1 port 9 figure 8.7 port 5 pin configuration 8.8.2 register configuration and description table 8.20 shows the port 9 register configuration. table 8.20 port 9 registers name abbrev. r/w initial value address port data register 9 pdr9 r/w h'ff h'ffdc port mode register 9 pmr9 r/w h'ffec 1. port data register 9 (pdr9) bit initial value read/write 7 1 6 1 5 p9 1 r/w 4 p9 1 r/w 3 p9 1 r/w 0 p9 1 r/w 2 p9 1 r/w 1 p9 1 r/w 543210 pdr9 is an 8-bit register that stores data for port 9 pins p9 5 to p9 0 . upon reset, pdr9 is initialized to h'ff.
159 2. port mode register 9 (pmr9) b it i nitial value r ead/write 7 1 6 1 5 1 4 1 3 pioff 0 r/w 0 pwm 1 0 r/w 2 w 1 pwm 2 0 r/w pmr9 is an 8-bit read/write register controlling the selection of the p9 0 and p9 1 pin functions. bit 3: p9 2 to p9 0 step-up circuit control (pioff) bit 3 turns the p9 2 to p9 0 step-up circuit on and off. bit 3 pioff description 0 large-current port step-up circuit is turned on (initial value) 1 large-current port step-up circuit is turned off note: when turning the step-up circuit on or off, the register must be rewritten only when the buffer nmos is off (port data is 1). when turning the step-up circuit on, first clear pioff to 0, then wait for the elapse of 30 system clock before turning the buffer nmos on (clearing port data to 0). without the elapse of the 30 system clock interval the step-up circuit will not start up, and it will not be possible for a large current to flow, making operation unstable. port 9 pin output low level permitted currents pin symbol test conditions min typ max pioff bit value p9 2 to p9 0 i ol v cc = 1.8 v to 5.5 v * 25 ma * 0 10 ma 1 p9 3 to p9 5 10 ma note: * for details, see section 14.2.2, dc characteristics. bit 2: reserved bit bit 2 is reserved; only 0 can be written to this bit.
160 bits 1 and 0: p9 n /pwm pin function switches these pins select whether pin p9n/pwmn+1 is used as p9n or as pwmn+1. bit n wkpn+1 description 0 functions as p9 n output pin (initial value) 1 functions as pwm n+1 output pin (n = 0 or 1) 8.8.3 pin functions table 8.21 shows the port 9 pin functions. table 8.21 port 9 pin functions pin pin functions and selection method p9 1 /pwm n+1 to p9 0 /pwm n+1 the pin function depends on bit wkp n in pmr5, bit pcr5 n in pcr5, and bits sgs3 to sgs0 in lpcr. (n = 1 or 0) pmr9 n 01 pin function p9 n output pin pwm n+1 output pin * : don t care 8.8.4 pin states table 8.22 shows the port 5 pin states in each operating mode. table 8.22 port 5 pin states pins reset sleep subsleep standby watch subactive active p9 5 to p9 2 p9 n /pwm n+1 to p9 n /pwm n+1 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional (n = 1 or 0)
161 8.9 port a 8.9.1 overview port a is a 4-bit i/o port, configured as shown in figure 8.8. pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 port a figure 8.8 port a pin configuration 8.9.2 register configuration and description table 8.23 shows the port a register configuration. table 8.23 port a registers name abbrev. r/w initial value address port data register a pdra r/w h'f0 h'ffdd port control register a pcra w h'f0 h'ffed 1. port data register a (pdra) b it i nitial value r ead/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 3210 pdra is an 8-bit register that stores data for port a pins pa 3 to pa 0 . if port a is read while pcra bits are set to 1, the values stored in pdra are read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read. upon reset, pdra is initialized to h'f0.
162 2. port control register a (pcra) bit initial value read/write 7 1 6 1 5 1 4 1 3 pcra 0 r/w 0 pcra 0 r/w 2 pcra 0 r/w 1 pcra 0 r/w 3210 pcra controls whether each of port a pins pa 3 to pa 0 functions as an input pin or output pin. setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcra and pdra settings are valid when the corresponding pins are designated for general-purpose input/output by lpcr. upon reset, pcra is initialized to h'f0. pcra is a write-only register, which is always read as all 1s.
163 8.9.3 pin functions table 8.24 shows the port a pin functions. table 8.24 port a pin functions pin pin functions and selection method pa 3 /com 4 the pin function depends on bit pcra 3 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 3 01 * pin function pa 3 input pin pa 3 output pin com 4 output pin pa 2 /com 3 the pin function depends on bit pcra 2 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 2 01 * pin function pa 2 input pin pa 2 output pin com 3 output pin pa 1 /com 2 the pin function depends on bit pcra 1 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 1 01 * pin function pa 1 input pin pa 1 output pin com 2 output pin pa 0 /com 1 the pin function depends on bit pcra 0 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 not 0000 pcra 0 01 * pin function pa 0 input pin pa 0 output pin com 1 output pin * : don t care
164 8.9.4 pin states table 8.25 shows the port a pin states in each operating mode. table 8.25 port a pin states pins reset sleep subsleep standby watch subactive active pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
165 8.10 port b 8.10.1 overview port b is a 4-bit input-only port, configured as shown in figure 8.9. pb 3 /an 3 /irq 1 port b pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 figure 8.9 port b pin configuration 8.10.2 register configuration and description table 8.26 shows the port b register configuration. table 8.26 port b register name abbrev. r/w initial value address port data register b pdrb r h'ffde port mode register b pmrb r/w h'f7 h'ffee 1. port data register b (pdrb) b it r ead/write 7 6 5 4 3 pb r 0 pb r 2 pb r 1 pb r 32 1 0 reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage.
166 2. port mode register b (pmrb) bit initial value read/write 7 1 6 1 5 1 4 1 3 irq1 0 r/w 0 1 2 1 1 1 pmrb is an 8-bit read/write register controlling the selection of the pb 3 pin function. upon reset, pmrb is initialized to h'f7. bits 7 to 4 and 2 to 0: reserved bits bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified. bit 3: pb 3 /an 3 / irq 1 pin function switch (irq1) these bits select whether pin pb 3 /an 3 / irq 1 is used as pb 3 /an 3 or as irq 1 . bit 3 irq1 description 0 functions as pb 3 /an 3 input pin (initial value) 1 functions as irq irq
167 8.10.3 pin functions table 8.27 shows the port b pin functions. table 8.27 port b pin functions pin pin functions and selection method pb 3 /an 3 / irq * pin function pb 3 input pin an 3 input pin irq 1 * : don t care
168 8.11 input/output data inversion function 8.11.1 overview with input pin rxd 32 and output pin txd 32 , the data can be handled in inverted form. scinv2 rxd 32 p4 1 /rxd 32 scinv3 txd 32 p4 2 /txd 32 figure 8.10 input/output data inversion function 8.11.2 register configuration and descriptions table 8.28 shows the registers used by the input/output data inversion function. table 8.28 register configuration name abbreviation r/w address serial port control register spcr r/w h'ff91 serial port control register (spcr) bit initial value read/write 7 1 6 1 5 spc32 0 r/w 4 w 3 scinv3 0 r/w 0 w 2 scinv2 0 r/w 1 w spcr is an 8-bit readable/writable register that performs rxd 32 and txd 32 pin input/output data inversion switching. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
169 bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 4: reserved bit bit 4 is reserved; only 0 can be written to this bit. bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0 txd 32 output data is not inverted (initial value) 1 txd 32 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0 rxd 32 input data is not inverted (initial value) 1 rxd 32 input data is inverted bits 1 and 0: reserved bits bits 1 and 0 are reserved; only 0 can be written to these bits. 8.11.3 note on modification of serial port control register when a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. when modifying a serial port control register, do so in a state in which data changes are invalidated.
170 8.12 application note 8.12.1 how to handle an unused pin if an i/o pin not used by the user system is floating, pull it up or down. ? if an unused pin is an input pin, handle it in one of the following ways: ? pull it up to v cc with an on-chip pull-up mos. ? pull it up to v cc with an external resistor of approximately 100 k ? . ? pull it down to v ss with an external resistor of approximately 100 k ? . ? for a pin also used by the a/d converter, pull it up to av cc . ? if an unused pin is an output pin, handle it in one of the following ways: ? set the output of the unused pin to high and pull it up to v cc with an on-chip pull-up mos. ? set the output of the unused pin to high and pull it up to v cc with an external resistor of approximately 100 k ? . ? set the output of the unused pin to low and pull it down to gnd with an external resistor of approximately 100 k ? .
171 section 9 timers 9.1 overview the h8/3802 series provides three timers: timers a, f, and an asynchronous event counter. the functions of these timers are outlined in table 9.1. table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks timer a ? 8-bit interval timer ?8 to ?8192 ? interval function (8 choices) ? time base w /128 (choice of 4 overflow periods) timer f ? 16-bit timer ? also usable as two independent8-bit timers. ? output compare output function ?4 to ?32, w /4 (4 choices) tmofl tmofh asynchro- nous event counter ? 16-bit counter ? also usable as two independent 8-bit counters ? counts events asynchronous to and ? ? can count asynchronous events (rising/falling/both edges) independ- ently of the mcu's internal clock ?2 to ?8 (3 choices) aevl aevh irqaec
172 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768 khz crystal oscillator is connected. 1. features features of timer a are given below. ? choice of eight internal clock sources (?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8). ? choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). ? an interrupt is requested when the counter overflows. ? use of module standby mode enables this module to be placed in standby mode independently when not used.
173 2. block diagram figure 9.1 shows a block diagram of timer a. psw internal data bus pss notation: 1/4 tma tca /128 w /8192, /4096, /2048, /512, /256, /128, /32, /8 irrta 8 * 64 * 128 * 256 * /4 w tma: tca: irrta: psw: pss: note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag prescaler w prescaler s w figure 9.1 block diagram of timer a
174 3. register configuration table 9.2 shows the register configuration of timer a. table 9.2 timer a registers name abbrev. r/w initial value address timer mode register a tma r/w h'ffb0 timer counter a tca r h'00 h'ffb1 clock stop register 1 ckstpr1 r/w h'ff h'fffa 9.2.2 register descriptions 1. timer mode register a (tma) bit initial value read/write 7 w 6 w 5 w 4 1 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w tma is an 8-bit read/write register for selecting the prescaler, and input clock. bits 7 to 5: reserved bits bits 7 to 5 are reserved; only 0 can be written to these bits. bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified.
175 bits 3 to 0: internal clock select (tma3 to tma0) bits 3 to 0 select the clock input to tca. the selection is made as follows. description bit 3 tma3 bit 2 tma2 bit 1 tma1 bit 0 tma0 prescaler and divider ratio or overflow period function 0 0 0 0 pss, /8192 (initial value) interval timer 1 pss, /4096 1 0 pss, /2048 1 pss, /512 1 0 0 pss, /256 1 pss, /128 1 0 pss, /32 1 pss, /8 1 0 0 0 psw, 1 s clock time 1 psw, 0.5 s base 1 0 psw, 0.25 s (when using 1 psw, 0.03125 s 32.768 khz) 1 0 0 psw and tca are reset 1 10 1
176 2. timer counter a (tca) bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 3. clock stop register 1 (ckstpr1) tfckstp tackstp s32ckstp adckstp 76543210 1 1111111 r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer a is described here. for details of the other bits, see the sections on the relevant modules. bit 0: timer a module standby mode control (tackstp) bit 0 controls setting and clearing of module standby mode for timer a. tackstp description 0 timer a is set to module standby mode 1 timer a module standby mode is cleared (initial value)
177 9.2.3 timer operation 1. interval timer operation when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see 3.3, interrupts. 2. real-time clock time base operation when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. 9.2.4 timer a operation states table 9.3 summarizes the timer a operation states. table 9.3 timer a operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tca interval reset functions functions halted halted halted halted halted clock time base reset functions functions functions functions functions halted halted tma reset functions retained retained functions retained retained retained note: when the real-time clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ (s) in the count cycle.
178 9.2.5 application note when bit 0 (tackstp) of the clock stop register 1 (ckstpr1) is cleared to 0, bit 3 (tma3) of the timer mode register a (tma) cannot be rewritten. set bit 0 (tackstp) of the clock stop register 1 (ckstpr1) to 1 before rewriting bit 3 (tma3) of the timer mode register a (tma). 9.3 timer f 9.3.1 overview timer f is a 16-bit timer with a built-in output compare function. timer f also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. timer f can also be used as two independent 8-bit timers (timer fh and timer fl). 1. features features of timer f are given below. ? /32, /16, /4, w/4) ? ? ? ? timer fh 8-bit timer * timer fl 8-bit timer/event counter internal clock choice of 4 ( /32, /16, /4, w/4) toggle output one compare match signal, output to tmofh pin(initial value settable) one compare match signal, output to tmofl pin (initial value settable) counter reset counter can be reset by compare match signal interrupt sources one compare match one overflow note: * when timer f operates as a 16-bit timer, it operates on the timer fl overflow signal. ? w/4 is selected as the internal clock, timer f can operate in watch mode, subactive mode, and subsleep mode. ?
179 2. block diagram figure 9.2 shows a block diagram of timer f. pss toggle circuit toggle circuit w /4 tmofl tmofh tcrf tcfl ocrfl tcfh ocrfh tcsrf comparator comparator match irrtfh irrtfl notation: tcrf: tcsrf: tcfh: tcfl: ocrfh: ocrfl: irrtfh: irrtfl: pss: timer control register f timer control/status register f 8-bit timer counter fh 8-bit timer counter fl output compare register fh output compare register fl timer fh interrupt request flag timer fl interrupt request flag prescaler s internal data bus figure 9.2 block diagram of timer f
180 3. pin configuration table 9.4 shows the timer f pin configuration. table 9.4 pin configuration name abbrev. i/o function timer fh output tmofh output timer fh toggle output pin timer fl output tmofl output timer fl toggle output pin 4. register configuration table 9.5 shows the register configuration of timer f. table 9.5 timer f registers name abbrev. r/w initial value address timer control register f tcrf w h'00 h'ffb6 timer control/status register f tcsrf r/w h'00 h'ffb7 8-bit timer counter fh tcfh r/w h'00 h'ffb8 8-bit timer counter fl tcfl r/w h'00 h'ffb9 output compare register fh ocrfh r/w h'ff h'ffba output compare register fl ocrfl r/w h'ff h'ffbb clock stop register 1 ckstpr1 r/w h'ff h'fffa
181 9.3.2 register descriptions 1. 16-bit timer counter (tcf) 8-bit timer counter (tcfh) 8-bit timer counter (tcfl) 15 14 13 12 11 10 9 8 tcf tcfh tcfl 76543210 0000000000000000 r/w bit: initial value: read/write: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcf is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters tcfh and tcfl. in addition to the use of tcf as a 16-bit counter with tcfh as the upper 8 bits and tcfl as the lower 8 bits, tcfh and tcfl can also be used as independent 8-bit counters. tcfh and tcfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see 9.3.3, cpu interface. tcfh and tcfl are each initialized to h'00 upon reset. a. 16-bit mode (tcf) when cksh2 is cleared to 0 in tcrf, tcf operates as a 16-bit counter. the tcf input clock is selected by bits cksl2 to cksl0 in tcrf. tcf can be cleared in the event of a compare match by means of cclrh in tcsrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf is 1 at this time, irrtfh is set to 1 in irr2, and if ientfh in ienr2 is 1, an interrupt request is sent to the cpu. b. 8-bit mode (tcfl/tcfh) when cksh2 is set to 1 in tcrf, tcfh and tcfl operate as two independent 8-bit counters. the tcfh (tcfl) input clock is selected by bits cksh2 to cksh0 (cksl2 to cksl0) in tcrf. tcfh (tcfl) can be cleared in the event of a compare match by means of cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, ovfh (ovfl) is set to 1 in tcsrf. if ovieh (oviel) in tcsrf is 1 at this time, irrtfh (irrtfl) is set to 1 in irr2, and if ientfh (ientfl) in ienr2 is 1, an interrupt request is sent to the cpu.
182 2. 16-bit output compare register (ocrf) 8-bit output compare register (ocrfh) 8-bit output compare register (ocrfl) 15 14 13 12 11 10 9 8 ocrf ocrfh ocrfl 76543210 1111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ocrf is a 16-bit read/write register composed of the two registers ocrfh and ocrfl. in addition to the use of ocrf as a 16-bit register with ocrfh as the upper 8 bits and ocrfl as the lower 8 bits, ocrfh and ocrfl can also be used as independent 8-bit registers. ocrfh and ocrfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see 9.3.3, cpu interface. ocrfh and ocrfl are each initialized to h'ff upon reset. a. 16-bit mode (ocrf) when cksh2 is cleared to 0 in tcrf, ocrf operates as a 16-bit register. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. at the same time, irrtfh is set to 1 in irr2. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin by means of compare matches, and the output level can be set (high or low) by means of tolh in tcrf. b. 8-bit mode (ocrfh/ocrfl) when cksh2 is set to 1 in tcrf, ocrfh and ocrfl operate as two independent 8-bit registers. ocrfh contents are compared with tcfh, and ocrfl contents are with tcfl. when the ocrfh (ocrfl) and tcfh (tcfl) values match, cmfh (cmfl) is set to 1 in tcsrf. at the same time, irrtfh (irrtfl) is set to 1 in irr2. if ientfh (ientfl) in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin (tmofl pin) by means of compare matches, and the output level can be set (high or low) by means of tolh (toll) in tcrf.
183 3. timer control register f (tcrf) tolh cksl2 cksl1 cksl0 cksh2 cksh1 cksh0 toll 76543210 0 0000000 w www www w bit: initial value: read/write: tcrf is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources and sets the output level of the tmofh and tmofl pins. tcrf is initialized to h'00 upon reset. bit 7: toggle output level h (tolh) bit 7 sets the tmofh pin output level. the output level is effective immediately after this bit is written. bit 7 tolh description 0 low level (initial value) 1 high level bits 6 to 4: clock select h (cksh2 to cksh0) bits 6 to 4 select the clock input to tcfh from among four internal clock sources or tcfl overflow. bit 6 cksh2 bit 5 cksh1 bit 4 cksh0 description 0 0 0 16-bit mode, counting on tcfl overflow signal (initial value) 001 010 0 1 1 use prohibited 1 0 0 internal clock: counting on /32 1 0 1 internal clock: counting on /16 1 1 0 internal clock: counting on /4 1 1 1 internal clock: counting on w/4
184 bit 3: toggle output level l (toll) bit 3 sets the tmofl pin output level. the output level is effective immediately after this bit is written. bit 3 toll description 0 low level (initial value) 1 high level bits 2 to 0: clock select l (cksl2 to cksl0) bits 2 to 0 select the clock input to tcfl from among four internal clock sources or external event input. bit 2 cksl2 bit 1 cksl1 bit 0 cksl0 description 0 0 0 non-operational (initial value) 0 0 1 use prohibited 010 011 1 0 0 internal clock: counting on /32 1 0 1 internal clock: counting on /16 1 1 0 internal clock: counting on /4 1 1 1 internal clock: counting on w/4
185 4. timer control/status register f (tcsrf) ovfh cmfl oviel cclrl cmfh ovieh cclrh ovfl 76543210 0 0000000 r/(w) * r/(w) * r/w r/w r/(w) * r/w r/w r/(w) * note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. bit: initial value: read/write: tcsrf is an 16-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. tcsrf is initialized to h'00 upon reset. bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcfh has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing conditions: (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting conditions: set when tcfh overflows from h ff to h 00 bit 6: compare match flag h (cmfh) bit 6 is a status flag indicating that tcfh has matched ocrfh. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 cmfh description 0 clearing conditions: (initial value) after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting conditions: set when the tcfh value matches the ocrfh value
186 bit 5: timer overflow interrupt enable h (ovieh) bit 5 selects enabling or disabling of interrupt generation when tcfh overflows. bit 5 ovieh description 0 tcfh overflow interrupt request is disabled (initial value) 1 tcfh overflow interrupt request is enabled bit 4: counter clear h (cclrh) in 16-bit mode, bit 4 selects whether tcf is cleared when tcf and ocrf match. in 8-bit mode, bit 4 selects whether tcfh is cleared when tcfh and ocrfh match. bit 4 cclrh description 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled (initial value) 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled bit 3: timer overflow flag l (ovfl) bit 3 is a status flag indicating that tcfl has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 3 ovfl description 0 clearing conditions: (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting conditions: set when tcfl overflows from h ff to h 00
187 bit 2: compare match flag l (cmfl) bit 2 is a status flag indicating that tcfl has matched ocrfl. this flag is set by hardware and cleared by software. it cannot be set by software. bit 2 cmfl description 0 clearing conditions: (initial value) after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting conditions: set when the tcfl value matches the ocrfl value bit 1: timer overflow interrupt enable l (oviel) bit 1 selects enabling or disabling of interrupt generation when tcfl overflows. bit 1 oviel description 0 tcfl overflow interrupt request is disabled (initial value) 1 tcfl overflow interrupt request is enabled bit 0: counter clear l (cclrl) bit 0 selects whether tcfl is cleared when tcfl and ocrfl match. bit 0 cclrl description 0 tcfl clearing by compare match is disabled (initial value) 1 tcfl clearing by compare match is enabled
188 5. clock stop register 1 (ckstpr1) tfckstp tackstp s32ckstp adckstp 76543210 1 1111111 r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer f is described here. for details of the other bits, see the sections on the relevant modules. bit 2: timer f module standby mode control (tfckstp) bit 2 controls setting and clearing of module standby mode for timer f. tfckstp description 0 timer f is set to module standby mode 1 timer f module standby mode is cleared (initial value)
189 9.3.3 cpu interface tcf and ocrf are 16-bit read/write registers, but the cpu is connected to the on-chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). in 16-bit mode, tcf read/write access and ocrf write access must be performed 16 bits at a time (using two consecutive byte-size mov instructions), and the upper byte must be accessed before the lower byte. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. in 8-bit mode, there are no restrictions on the order of access. 1. write access write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte.
190 figure 9.3 shows an example in which h'aa55 is written to tcf. write to upper byte cpu (h'aa) temp (h'aa) tcfh ( ) tcfl ( ) bus interface module data bus write to lower byte cpu (h'55) temp (h'aa) tcfh (h'aa) tcfl (h'55) bus interface module data bus figure 9.3 write access to tcr (cpu tcf)
191 2. read access in access to tcf, when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower-byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. in access to ocrf, when the upper byte is read the upper-byte data is transferred directly to the cpu. when the lower byte is read, the lower-byte data is transferred directly to the cpu. figure 9.4 shows an example in which tcf is read when it contains h'aaff. read upper byte cpu (h'aa) temp (h'ff) tcfh (h'aa) tcfl (h'ff) bus interface module data bus read lower byte cpu (h'ff) temp (h'ff) tcfh (ab)* tcfl (00)* bus interface module data bus note: * h'ab00 if counter has been updated once. figure 9.4 read access to tcf (tcf cpu)
192 9.3.4 operation timer f is a 16-bit counter that increments on each input clock pulse. the timer f value is constantly compared with the value set in output compare register f, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. timer f can also function as two independent 8-bit timers. 1. timer f operation timer f has two operating modes, 16-bit timer mode and 8-bit timer mode. the operation in each of these modes is described below. a. operation in 16-bit timer mode when cksh2 is cleared to 0 in timer control register f (tcrf), timer f operates as a 16-bit timer. following a reset, timer counter f (tcf) is initialized to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control/status register f (tcsrf) to h'00. the timer f operating clock can be selected from three internal clocks output by prescaler s by means of bits cksl2 to cksl0 in tcrf. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu, and at the same time, tmofh pin output is toggled. if cclrh in tcsrf is 1, tcf is cleared. tmofh pin output can also be set by tolh in tcrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf and ientfh in ienr2 are both 1, an interrupt request is sent to the cpu. b. operation in 8-bit timer mode when cksh2 is set to 1 in tcrf, tcf operates as two independent 8-bit timers, tcfh and tcfl. the tcfh/tcfl input clock is selected by cksh2 to cksh0/cksl2 to cksl0 in tcrf. when the ocrfh/ocrfl and tcfh/tcfl values match, cmfh/cmfl is set to 1 in tcsrf. if ientfh/ientfl in ienr2 is 1, an interrupt request is sent to the cpu, and at the same time, tmofh pin/tmofl pin output is toggled. if cclrh/cclrl in tcsrf is 1, tcfh/tcfl is cleared. tmofh pin/tmofl pin output can also be set by tolh/toll in tcrf. when tcfh/tcfl overflows from h'ff to h'00, ovfh/ovfl is set to 1 in tcsrf. if ovieh/oviel in tcsrf and ientfh/ientfl in ienr2 are both 1, an interrupt request is sent to the cpu.
193 2. tcf increment timing tcf is incremented by clock input (internal clock input). bits cksh2 to cksh0 or cksl2 to cksl0 in tcrf select one of four internal clock sources ( /32, /16, /4, or w/4) created by dividing the system clock ( or w). 3. tmofh/tmofl output timing in tmofh/tmofl output, the value set in tolh/toll in tcrf is output. the output is toggled by the occurrence of a compare match. figure 9.5 shows the output timing. count input clock tcf ocrf tmofh tmofl compare match signal nn n n n+1 n+1 figure 9.5 tmofh/tmofl output timing
194 4. tcf clear timing tcf can be cleared by a compare match with ocrf. 5. timer overflow flag (ovf) set timing ovf is set to 1 when tcf overflows from h'ffff to h'0000. 6. compare match flag set timing the compare match flag (cmfh or cmfl) is set to 1 when the tcf and ocrf values match. the compare match signal is generated in the last state during which the values match (when tcf is updated from the matching value to a new value). when tcf matches ocrf, the compare match signal is not generated until the next counter clock. 7. timer f operation modes timer f operation modes are shown in table 9.6. table 9.6 timer f operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby tcf reset functions functions functions/ halted * functions/ halted * functions/ halted * halted halted ocrf reset functions held held functions held held held tcrf reset functions held held functions held held held tcsrf reset functions held held functions held held held note: * when w /4 is selected as the tcf internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode, watch mode, or subsleep mode, w /4 must be selected as the internal clock. the counter will not operate if any other internal clock is selected.
195 9.3.5 application notes the following types of contention and operation can occur when timer f is used. 1. 16-bit timer mode in toggle output, tmofh pin output is toggled when all 16 bits match and a compare match signal is generated. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. tmofl pin output is unstable in 16-bit mode, and should not be used; the tmofl pin should be used as a port pin. if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated. compare match flag cmfl is set if the setting conditions for the lower 8 bits are satisfied. when tcf overflows, ovfh is set. ovfl is set if the setting conditions are satisfied when the lower 8 bits overflow. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 2. 8-bit timer mode a. tcfh, ocrfh in toggle output, tmofh pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. if an ocrfh write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write and overflow signal output occur simultaneously, the overflow signal is not output. b. tcfl, ocrfl in toggle output, tmofl pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, toll data is output to the tmofl pin as a result of the tcrf write.
196 if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 3. clear timer fh, timer fl interrupt request flags (irrtfh, irrtfl), timer overflow flags h, l (ovfh, ovfl) and compare match flags h, l (cmfh, cmfl) when w/4 is selected as the internal clock, interrupt factor generation signal will be operated with w and the signal will be outputted with w width. and, overflow signal and compare match signal are controlled with 2 cycles of w signals. those signals are outputted with 2 cycles width of w (figure 9.6) in active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of interrupt factor generation signal , same interrupt request flag is set. (figure 9.6 1) and, you cannot be cleared timer overflow flag and compare match flag during the term of validity of overflow signal and compare match signal . for interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer fh, timer fl interrupt might be repeated. (figure 9.6 2) therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. and, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register f (tcsrf) after the time that calculated with below (1) formula. for st of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of rte instruction when mulxu, divxu instruction is not used, 14 states when mulxu, divxu instruction is used) in subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. the term of validity of interrupt factor generation signal = 1 cycle of w + waiting time for completion of executing instruction + interrupt time synchronized with = 1/ w + st ) + (2/ ) (second).....(1) st: executing number of execution states method 1 is recommended to operate for time efficiency. method 1 1. prohibit interrupt in interrupt handling routine (set ienfh, ienfl to 0). 2. after program process returned normal handling, clear interrupt request flags (irrtfh, irrtfl) after more than that calculated with (1) formula.
197 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). 4. operate interrupt permission (set ienfh, ienfl to 1). method 2 1. set interrupt handling routine time to more than time that calculated with (1) formula. 2. clear interrupt request flags (irrtfh, irrtfl) at the end of interrupt handling routine. 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). all above attentions are also applied in 16-bit mode and 8-bit mode. program process w interrupt request flag (irrtfh, irrtfl) interrupt factor generation signal (internal signal, nega-active) overflow signal, compare match signal (internal signal, nega-active) interrupt interrupt normal interrupt request flag clear interrupt request flag clear 1 2 figure 9.6 clear interrupt request flag when interrupt factor generation signal is valid 4. timer counter (tcf) read/write when w/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on tcf is impossible. and, when read tcf, as the system clock and internal clock are mutually asynchronous, tcf synchronizes with synchronization circuit. this results in a maximum tcf read value error of w/4 before read/write. in subactive mode, even w/4 is selected as the internal clock, normal read/write tcf is possible.
198 9.4 asynchronous event counter (aec) 9.4.1 overview the asynchronous event counter is incremented by external event clock or internal clock input. 1. features features of the asynchronous event counter are given below. can count asynchronous events can count external events input asynchronously without regard to the operation of base clocks and sub . the counter has a 16-bit configuration, enabling it to count up to 65536 (2 16 ) events. ? ? ? ? ? ? /2, /4, or /8 can be selected as the prescaler output clock. ? ? ? ?
199 2. block diagram figure 9.7 shows a block diagram of the asynchronous event counter. aevh aevl irqaec iecpwm eccr pss eccsr ovh ovl ecpwcrh ecpwdrh aegsr ecpwcrl internal data bus ecpwdrl ech (8 bit) ck ecl (8 bit) ck irrec to cpu interrupt (irrec2) edge sensing circuit edge sensing circuit edge sensing circuit pwm waveform generator /2 /4, /8 /2, /4, /8, /16, /32, /64 notation ecpwcrh: event counter pwm compare register h ecpwdrh: event counter pwm data register h aegsr: input pin edge selection register eccsr: event counter control/status register ech: event counter h ecl: event counter l ecpwcrl: event counter pwm compare register l ecpwdrl: event counter pwm data register l eccr: event counter control register figure 9.7 block diagram of asynchronous event counter
200 3. pin configuration table 9.7 shows the asynchronous event counter pin configuration. table 9.7 pin configuration name abbrev. i/o function asynchronous event input h aevh input event input pin for input to event counter h asynchronous event input l aevl input event input pin for input to event counter l event input enable interrupt input irqaec input input pin for interrupt enabling event input 4. register configuration table 9.8 shows the register configuration of the asynchronous event counter. table 9.8 asynchronous event counter registers name abbrev. r/w initial value address event counter pwm compare register h ecpwcrh r/w h'ff h'ff8c event counter pwm compare register l ecpwcrl r/w h'ff h'ff8d event counter pwm data register h ecpwdrh w h'00 h'ff8e event counter pwm data register l ecpwdrl w h'00 h'ff8f input pin edge selection register aegsr r/w h'00 h'ff92 event counter control register eccr r/w h'00 h'ff94 event counter control/status register eccsr r/w h'00 h'ff95 event counter h ech r h'00 h'ff96 event counter l ecl r h'00 h'ff97 clock stop register 2 ckstp2 r/w h'ff h'fffb
201 9.4.2 register configurations 1. event counter pwm compare register h (ecpwcrh) b it i nitial value r ead/write 7 ecpwcrh7 1 r/w 6 ecpwcrh6 1 r/w 5 ecpwcrh5 1 r/w 4 ecpwcrh4 1 r/w 3 ecpwcrh3 1 r/w 0 ecpwcrh0 1 r/w 2 ecpwcrh2 1 r/w 1 ecpwcrh1 1 r/w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwcrh should not be modified. when changing the conversion period, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwcrh. ecpwcrh is an 8-bit read/write register that sets the event counter pwm waveform conversion period. 2. event counter pwm compare register l (ecpwcrl) b it i nitial value r ead/write 7 ecpwcrl7 1 r/w 6 ecpwcrl6 1 r/w 5 ecpwcrl5 1 r/w 4 ecpwcrl4 1 r/w 3 ecpwcrl3 1 r/w 0 ecpwcrl0 1 r/w 2 ecpwcrl2 1 r/w 1 ecpwcrl1 1 r/w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwcrl should not be modified. when changing the conversion period, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwcrl. ecpwcrl is an 8-bit read/write register that sets the event counter pwm waveform conversion period.
202 3. event counter pwm data register h (ecpwdrh) bit initial value read/write 7 ecpwdrh7 0 w 6 ecpwdrh6 0 w 5 ecpwdrh5 0 w 4 ecpwdrh4 0 w 3 ecpwdrh3 0 w 0 ecpwdrh0 0 w 2 ecpwdrh2 0 w 1 ecpwdrh1 0 w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwdrh should not be modified. when changing the data, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwdrh. ecpwdrh is an 8-bit write-only register that controls event counter pwm waveform generator data. 4. event counter pwm data register l (ecpwdrl) bit initial value read/write 7 ecpwdrl7 0 w 6 ecpwdrl6 0 w 5 ecpwdrl5 0 w 4 ecpwdrl4 0 w 3 ecpwdrl3 0 w 0 ecpwdrl0 0 w 2 ecpwdrl2 0 w 1 ecpwdrl1 0 w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwdrl should not be modified. when changing the data, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwdrl. ecpwdrl is an 8-bit write-only register that controls event counter pwm waveform generator data. 5. input pin edge selection register (aegsr) bit initial value read/write 7 ahegs1 0 r/w 6 ahegs0 0 r/w 5 alegs1 0 r/w 4 alegs0 0 r/w 3 aiegs1 0 r/w 0 0 r/w 2 aiegs0 0 r/w 1 ecpwme 0 r/w aegsr is an 8-bit read/write register that selects rising, falling, or both edge sensing for the aevh, aevl, and irqaec pins.
203 bits 7 and 6: aec edge select h bits 7 and 6 select rising, falling, or both edge sensing for the aevh pin. bit 7 ahegs1 bit 6 ahegs0 description 0 0 falling edge on aevh pin is sensed (initial value) 1 rising edge on aevh pin is sensed 1 0 both edges on aevh pin are sensed 1 use prohibited bits 5 and 4: aec edge select l bits 5 and 4 select rising, falling, or both edge sensing for the aevl pin. bit 5 alegs1 bit 4 alegs0 description 0 0 falling edge on aevl pin is sensed (initial value) 1 rising edge on aevl pin is sensed 1 0 both edges on aevl pin are sensed 1 use prohibited bits 3 and 2: irqaec edge select bits 3 and 2 select rising, falling, or both edge sensing for the irqaec pin. bit 3 aiegs1 bit 2 aiegs0 description 0 0 falling edge on irqaec pin is sensed (initial value) 1 rising edge on irqaec pin is sensed 1 0 both edges on irqaec pin are sensed 1 use prohibited
204 bit 1: event counter pwm enable bit 1 controls enabling/disabling of event counter pwm and selection/deselection of irqaec. bit 1 ecpwme description 0 aec pwm halted, irqaec selected (initial value) 1 aec pwm operation enabled, irqaec deselected bit 0: reserved bit bit 0 is a readable/writable reserved bit. it is initialized to 0 by a reset. note: do not set this bit to 1. 6. event counter control register (eccr) bit initial value read/write 7 ackh1 0 r/w 6 ackh0 0 r/w 5 ackl1 0 r/w 4 ackl0 0 r/w 3 pwck2 0 r/w 0 0 r/w 2 pwck1 0 r/w 1 pwck0 0 r/w eccr performs counter input clock and irqaec/iecpwm control. bits 7 and 6: aec clock select h (ackh1, ackh0) bits 7 and 6 select the clock used by ech. bit 7 ackh1 bit 6 ackh0 description 0 0 aevh pin input (initial value) 1 /2 10 /4 1 /8
205 bits 5 and 4: aec clock select l (ackl1, ackl0) bits 5 and 4 select the clock used by ecl. bit 5 ackl1 bit 4 ackl0 description 0 0 aevl pin input (initial value) 1 /2 10 /4 1 /8 bits 3 to 1: event counter pwm clock select (pwck2, pwck1, pwck0) bits 3 to 1 select the event counter pwm clock. bit 3 pwck2 bit 2 pwck1 bit 1 pwck0 description 000 /2 (initial value) 1 /4 10 /8 1 /16 1 * 0 /32 1 /64 * : don t care bit 0: reserved bit bit 0 is a readable/writable reserved bit. it is initialized to 0 by a reset. note: do not set this bit to 1. 7. event counter control/status register (eccsr) ovh cuel crch crcl ovl ch2 cueh 76543210 0 0000000 r/w * r/w r/w r/w r/w * r/w r/w r/w bit note: * bits 7 and 6 can only be written with 0, for flag clearing. initial value read/write
206 eccsr is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. eccsr is initialized to h'00 upon reset. bit 7: counter overflow flag h (ovh) bit 7 is a status flag indicating that ech has overflowed from h'ff to h'00. this flag is set when ech overflows. it is cleared by software but cannot be set by software. ovh is cleared by reading it when set to 1, then writing 0. when ech and ecl are used as a 16-bit event counter with ch2 cleared to 0, ovh functions as a status flag indicating that the 16-bit event counter has overflowed from h'ffff to h'0000. bit 7 ovh description 0 ech has not overflowed (initial value) clearing conditions: after reading ovh = 1, cleared by writing 0 to ovh 1 ech has overflowed setting conditions: set when ech overflows from h ff to h 00 bit 6: counter overflow flag l (ovl) bit 6 is a status flag indicating that ecl has overflowed from h'ff to h'00. this flag is set when ecl overflows. it is cleared by software but cannot be set by software. ovl is cleared by reading it when set to 1, then writing 0. bit 6 ovl description 0 ecl has not overflowed (initial value) clearing conditions: after reading ovl = 1, cleared by writing 0 to ovl 1 ecl has overflowed setting conditions: set when ecl overflows from h'ff to h'00 while ch2 is set to 1 bit 5: reserved bit bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset.
207 bit 4: channel select (ch2) bit 4 selects whether ech and ecl are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. when ch2 is cleared to 0, ech and ecl function as a 16-bit event counter which is incremented each time an event clock is input to the aevl pin. in this case, the overflow signal from ecl is selected as the ech input clock. when ch2 is set to 1, ech and ecl function as independent 8-bit event counters which are incremented each time an event clock is input to the aevh or aevl pin, respectively. bit 4 ch2 description 0 ech and ecl are used together as a single-channel 16-bit event counter (initial value) 1 ech and ecl are used as two independent 8-bit event counter channels bit 3: count-up enable h (cueh) bit 3 enables event clock input to ech. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ech value is held. the aevh pin or the ecl overflow signal can be selected as the event clock source by bit ch2. bit 3 cueh description 0 ech event clock input is disabled (initial value) ech value is held 1 ech event clock input is enabled bit 2: count-up enable l (cuel) bit 3 enables event clock input to ecl. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ecl value is held. bit 2 cuel description 0 ecl event clock input is disabled (initial value) ecl value is held 1 ecl event clock input is enabled
208 bit 1: counter reset control h (crch) bit 1 controls resetting of ech. when this bit is cleared to 0, ech is reset. when 1 is written to this bit, the counter reset is cleared and the ech count-up function is enabled. bit 1 crch description 0 ech is reset (initial value) 1 ech reset is cleared and count-up function is enabled bit 0: counter reset control l (crcl) bit 0 controls resetting of ecl. when this bit is cleared to 0, ecl is reset. when 1 is written to this bit, the counter reset is cleared and the ecl count-up function is enabled. bit 0 crcl description 0 ecl is reset (initial value) 1 ecl reset is cleared and count-up function is enabled 8. event counter h (ech) ech7 ech2 ech1 ech0 ech6 ech5 ech4 ech3 76543210 0 0000000 r rrr rrr r bit initial value read/write ech is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ecl. either the external asynchronous event aevh pin or the overflow signal from lower 8-bit counter ecl can be selected as the input clock source. ech can be cleared to h'00 by software, and is also initialized to h'00 upon reset.
209 9. event counter l (ecl) ecl is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ech. the event clock from the external asynchronous event aevl pin, or /2, /4, or /8, is used as the input clock source. ecl can be cleared to h'00 by software, and is also initialized to h'00 upon reset. ecl7 ecl2 ecl1 ecl0 ecl6 ecl5 ecl4 ecl3 76543210 0 0000000 r rrr rrr r bit initial value read/write 10. clock stop register 2 (ckstpr2) pw1ckstp ldckstp pw2ckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the asynchronous event counter is described here. for details of the other bits, see the sections on the relevant modules. bit 3: asynchronous event counter module standby mode control (aeckstp) bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. aeckstp description 0 asynchronous event counter is set to module standby mode 1 asynchronous event counter module standby mode is cleared (initial value)
210 9.4.3 operation 1. 16-bit event counter operation when bit ch2 is cleared to 0 in eccsr, ech and ecl operate as a 16-bit event counter. any of four input clock sources ? /2, /4, /8, or aevl pin input can be selected by means of bits ackl1 and ackl0 in eccr. when aevl pin input is selected, input sensing is selected with bits alegs1 and alegs0. the input clock is enabled only when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 9.8 shows an example of the software processing when ech and ecl are used as a 16-bit event counter. start end clear ch2 to 0 set ackl1 0 and alegs1 0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 figure 9.8 example of software processing when using ech and ecl as 16-bit event counter as ch2 is cleared to 0 by a reset, ech and ecl operate as a 16-bit event counter after a reset, and as ackl1 and ackl0 are cleared to 00, the operating clock is asynchronous event input from the aevl pin (using falling edge sensing). when the next clock is input after the count value reaches h'ff in both ech and ecl, ech and ecl overflow from h'ffff to h'0000, the ovh flag is set to 1 in eccsr, the ech and ecl count values each return to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu.
211 2. 8-bit event counter operation when bit ch2 is set to 1 in eccsr, ech and ecl operate as independent 8-bit event counters. /2, /4, /8, or aevh pin input can be selected as the input clock source for ech by means of bits ackh1 and ackh0 in eccr, and /2, /4, /8, or aevl pin input can be selected as the input clock source for ecl by means of bits ackl1 and ackl0 in eccr. input sensing is selected with bits ahegs1 and ahegs0 when aevh pin input is selected, and with bits alegs1 and alegs0 when aevl pin input is selected. the input clock is enabled only when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 9.9 shows an example of the software processing when ech and ecl are used as 8-bit event counters. start end set ch2 to 1 set ackh1 0, ackl1 0, ahegs1 0, alegs1 0 clear cueh, cuel, crch, and crcl to 0 clear ovh to 0 set cueh, cuel, crch, and crcl to 1 figure 9.9 example of software processing when using ech and ecl as 8-bit event counters ech and ecl can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.9. when the next clock is input after the ech count value reaches h'ff, ech overflows, the ovh flag is set to 1 in eccsr, the ech count value returns to h'00, and counting up is restarted. similarly, when the next clock is input after the ecl count value reaches h'ff, ecl overflows, the ovl flag is set to 1 in eccsr, the ecl count value returns to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu.
212 3. irqaec operation when ecpwme in aegsr is 0, the ech and ecl input clocks are enabled only when irqaec is high. when irqaec is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled from outside by controlling irqaec. in this case, ech and ecl cannot be controlled individually. irqaec can also operate as an interrupt source. in this case the vector number is 6 and the vector addresses are h'000c and h'000d. interrupt enabling is controlled by ienec2 in ienr1. when an irqaec interrupt is generated, irr1 interrupt request flag irrec2 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge sensing can be selected for the irqaec input pin with bits aiags1 and aiags0 in aegsr. 4. event counter pwm operation when ecpwme in aegsr is 1, the ech and ecl input clocks are enabled only when event counter pwm output (iecpwm) is high. when iecpwm is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled cyclically from outside by controlling event counter pwm. in this case, ech and ecl cannot be controlled individually. iecpwm can also operate as an interrupt source. in this case the vector number is 6 and the vector addresses are h'000c and h'000d. interrupt enabling is controlled by ienec2 in ienr1. when an iecpwm interrupt is generated, irr1 interrupt request flag irrec2 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge detection can be selected for iecpwm interrupt sensing with bits aiags1 and aiags0 in aegsr. figure 9.10 and table 9.9 show examples of event counter pwm operation.
213 t off = t (n dr +1) t on t cm = t (n cm +1) t on : clock input enabled time t off : clock input disabled time t cm : one conversion period t : ecpwm input clock cycle n dr : value of ecpwdrh and ecpwdrl fixed high when ndr = h'ffff n cm : value of ecpwcrh and ecpwcrl figure 9.10 event counter operation waveform note: n dr and n cm above must be set so that n dr < n cm . if the settings do not satisfy this condition, do not set ecpwme to 1 in aegsr. table 9.9 examples of event counter pwm operation conditions: f osc = 4 mhz, f = 2 mhz, high-speed active mode, ecpwcr value (n cm ) = h'7a11, ecpwdr value (n dr ) = h'16e3 clock source selection clock source cycle (t) * ecpwmcr value (n cm ) ecpwmdr value (n dr ) t off = t (n dr + 1) t cm = t (n cm + 1) t on = t cm ?t off /2 1 s h'7a11 h'16e3 5.86 ms 31.25 ms 25.39 ms /4 2 s d'31249 d'5859 11.72 ms 62.5 ms 50.78 ms /8 4 s 23.44 ms 125.0 ms 101.56 ms /16 8 s 46.88 ms 250.0 ms 203.12 ms /32 16 s 93.76 ms 500.0 ms 406.24 ms /64 32 s 187.52 ms 1000.0 ms 812.48 ms note: * t off minimum width 5. clock input enable/disable function operation the clock input to the event counter can be controlled by the irqaec pin when ecpwme in aegsr is 0, and by event counter pwm output iecpwm when ecpwme in aegsr is 1. as this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending the irqaec or iecpwm timing. figure 9.11 shows an example of the operation of this function.
214 clock stopped n+2 n+3 n+4 n+5 n+6 n n+1 edge generated by clock return input event irqaec or iecpwm actually counted clock source counter value figure 9.11 example of clock control operation 9.4.4 asynchronous event counter operation modes asynchronous event counter operation modes are shown in table 9.10. table 9.10 asynchronous event counter operation modes operation mode reset active sleep watch subactive subsleep standby module standby aegsr reset functions functions held * 1 functions functions held * 1 held eccr reset functions functions held * 1 functions functions held * 1 held eccsr reset functions functions held * 1 functions functions held * 1 held ech reset functions functions functions * 1 * 2 functions * 2 functions * 2 functions * 1 * 2 halted ecl reset functions functions functions * 1 * 2 functions * 2 functions * 2 functions * 1 * 2 halted ieqaec reset functions functions held * 3 functions functions held * 3 held * 4 event counter pwm reset functions functions held held held held held notes: 1. when an asynchronous external event is input, the counter increments but the counter overflow h/l flags are not affected. 2. operates when asynchronous mode external events are selected; halted and retained otherwise. 3. clock control by irqaec operates, but interrupts do not. 4. as the clock is stopped in module standby mode, irqaec has no effect.
215 9.4.5 application notes 1. when reading the values in ech and ecl, first clear bits cueh and cuel to 0 in eccsr to prevent asynchronous event input to the counter. the correct value will not be returned if the event counter increments while being read. 2. use a clock with a frequency of up to 16 mhz for input to the aevh and aevl pins, and ensure that the high and low widths of the clock are at least 30 ns. the duty cycle is immaterial. mode maximum aevh/aevl pin input clock frequency active (high-speed), sleep (high-speed) 16 mhz active (medium-speed), sleep (medium-speed) ( /16) ( /32) ( /64) f osc = 1 mhz to 4 mhz ( /128) 2 f osc f osc 1/2 f osc 1/4 f osc watch, subactive, subsleep, standby ( w/2) ( w/4) w = 32.768 khz or 38.4 khz ( w/8) 1000 khz 500 khz 250 khz 3. when aec uses with 16-bit mode, set cueh in eccsr to 1 first, set crch in eccsr to 1 second, or set both cueh and crch to 1 at same time before clock entry. while aec is operating on 16-bit mode, do not change cueh. otherwise, ech will be miscounted up. 4. when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwcrh, ecpwcrl, ecpwdrh, and ecpwdrl should not be modified. when changing the data, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying these registers. 5. the event counter pwm data register and event counter pwm compare register must be set so that event counter pwm data register < event counter pwm compare register. if the settings do not satisfy this condition, do not set ecpwme to 1 in aegsr. 6. as synchronization is established internally when an irqaec interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
216
217 section 10 serial communication interface 10.1 overview the h8/3802 series is provided with one serial communication interface, sci3. serial communication interface 3 (sci3) can carry out serial data communication in either asynchronous or synchronous mode. it is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 10.1.1 features features of sci3 are listed below. ? choice of asynchronous or synchronous mode for serial data communication ? asynchronous mode serial data communication is performed asynchronously, with synchronization provided character by character. in this mode, serial data can be exchanged with standard asynchronous communication lsis such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a multiprocessor communication function is also provided, enabling serial data communication among processors. there is a choice of 16 data transfer formats. data length 7, 8, 5 bits stop bit length 1 or 2 bits parity even, odd, or none multiprocessor bit 1 or 0 receive error detection parity, overrun, and framing errors break detection break detected by reading the rxd 32 pin level directly when a framing error occurs
218 ? synchronous mode serial data communication is synchronized with a clock. in his mode, serial data can be exchanged with another lsi that has a synchronous communication function. data length 8 bits receive error detection overrun errors ? full-duplex communication separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. the transmission and reception units are both double-buffered, allowing continuous transmission and reception. ? on-chip baud rate generator, allowing any desired bit rate to be selected ? choice of an internal or external clock as the transmit/receive clock source ? six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error
219 10.1.2 block diagram figure 10.1 shows a block diagram of sci3. clock txd rxd sck brr smr scr3 ssr tdr rdr tsr rsr spcr transmit/receive control circuit internal data bus notation: rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: spcr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter serial port control register interrupt request (tei, txi, rxi, eri) 32 internal clock (?64, ?16, ?/2, ? external clock brc baud rate generator figure 10.1 sci3 block diagram
220 10.1.3 pin configuration table 10.1 shows the sci3 pin configuration. table 10.1 pin configuration name abbrev. i/o function sci3 clock sck 32 i/o sci3 clock input/output sci3 receive data input rxd 32 input sci3 receive data input sci3 transmit data output txd 32 output sci3 transmit data output 10.1.4 register configuration table 10.2 shows the sci3 register configuration. table 10.2 registers name abbrev. r/w initial value address serial mode register smr r/w h'00 h'ffa8 bit rate register brr r/w h'ff h'ffa9 serial control register 3 scr3 r/w h'00 h'ffaa transmit data register tdr r/w h'ff h'ffab serial data register ssr r/w h'84 h'ffac receive data register rdr r h'00 h'ffad transmit shift register tsr protected receive shift register rsr protected bit rate counter brc protected clock stop register 1 ckstpr1 r/w h'ff h'fffa serial port control register spcr r/w h'ff91
221 10.2 register descriptions 10.2.1 receive shift register (rsr) bit read/write 7 6 5 4 3 0 2 1 rsr is a register used to receive serial data. serial data input to rsr from the rxd 32 pin is set in the order in which it is received, starting from the lsb (bit 0), and converted to parallel data. when one byte of data is received, it is transferred to rdr automatically. rsr cannot be read or written directly by the cpu. 10.2.2 receive data register (rdr) bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r rdr is an 8-bit register that stores received serial data. when reception of one byte of data is finished, the received data is transferred from rsr to rdr, and the receive operation is completed. rsr is then able to receive data. rsr and rdr are double-buffered, allowing consecutive receive operations. rdr is a read-only register, and cannot be written by the cpu. rdr is initialized to h'00 upon reset, and in standby, module standby or watch mode.
222 10.2.3 transmit shift register (tsr) b it r ead/write 7 6 5 4 3 0 2 1 tsr is a register used to transmit serial data. transmit data is first transferred from tdr to tsr, and serial data transmission is carried out by sending the data to the txd 32 pin in order, starting from the lsb (bit 0). when one byte of data is transmitted, the next byte of transmit data is transferred to tdr, and transmission started, automatically. data transfer from tdr to tsr is not performed if no data has been written to tdr (if bit tdre is set to 1 in the serial status register (ssr)). tsr cannot be read or written directly by the cpu. 10.2.4 transmit data register (tdr) b it i nitial value r ead/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w tdr is an 8-bit register that stores transmit data. when tsr is found to be empty, the transmit data written in tdr is transferred to tsr, and serial data transmission is started. continuous transmission is possible by writing the next transmit data to tdr during tsr serial data transmission. tdr can be read or written by the cpu at any time. tdr is initialized to h'ff upon reset, and in standby, module standby, or watch mode.
223 10.2.5 serial mode register (smr) bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 pm 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w smr is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. smr can be read or written by the cpu at any time. smr is initialized to h'00 upon reset, and in standby, module standby, or watch mode. bit 7: communication mode (com) bit 7 selects whether sci3 operates in asynchronous mode or synchronous mode. bit 7 com description 0 asynchronous mode (initial value) 1 synchronous mode bit 6: character length (chr) bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. in synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. bit 6 chr description 0 8-bit data/5-bit data * 2 (initial value) 1 7-bit data * 1 /5-bit data * 2 notes: 1. when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 2. when 5-bit data is selected, set both pe and mp to 1. the three most significant bits (bits 7, 6, and 5) of tdr are not transmitted.
224 bit 5: parity enable (pe) bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. in synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. bit 5 pe description 0 parity bit addition and checking disabled * 2 (initial value) 1 parity bit addition and checking enabled * 1/ * 2 notes: 1. when pe is set to 1, even or odd parity, as designated by bit pm, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit pm. 2. for the case where 5-bit data is selected, see table 10.11. bit 4: parity mode (pm) bit 4 selects whether even or odd parity is to be used for parity addition and checking. the pm bit setting is only valid in asynchronous mode when bit pe is set to 1, enabling parity bit addition and checking. the pm bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. bit 4 pm description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. when odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number.
225 bit 3: stop bit length (stop) bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. when synchronous mode is selected the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. in transmission, two 1 bits (stop bits) are added at the end of a transmit character. in reception, only the first of the received stop bits is checked, irrespective of the stop bit setting. if the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. bit 2: multiprocessor mode (mp) bit 2 enables or disables the multiprocessor communication function. when the multiprocessor communication function is enabled, the parity settings in the pe and pm bits are invalid. the mp bit setting is only valid in asynchronous mode. when synchronous mode is selected the mp bit should be set to 0. for details on the multiprocessor communication function, see 10.3.4, multiprocessor communication function. bit 2 mp description 0 multiprocessor communication function disabled * (initial value) 1 multiprocessor communication function enabled * note: * for the case where 5-bit data is selected, see table 10.11.
226 bits 1 and 0: clock select 1, 0 (cks1, cks0) bits 1 and 0 choose ?64, ?16, ?/2, or ?as the clock source for the baud rate generator. for the relation between the clock source, bit rate register setting, and baud rate, see 8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 00 clock (initial value) 01 w/2 clock * 1 / w clock * 2 10 /16 clock 11 /64 clock notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode 3. in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 10.2.6 serial control register 3 (scr3) b it i nitial value r ead/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w scr3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. scr3 can be read or written by the cpu at any time. scr3 is initialized to h'00 upon reset, and in standby, module standby or watch mode.
227 bit 7: transmit interrupt enable (tie) bit 7 selects enabling or disabling of the transmit data empty interrupt request (txi) when transmit data is transferred from the transmit data register (tdr) to the transmit shift register (tsr), and bit tdre in the serial status register (ssr) is set to 1. txi can be released by clearing bit tdre or bit tie to 0. bit 7 tie description 0 transmit data empty interrupt request (txi) disabled (initial value) 1 transmit data empty interrupt request (txi) enabled bit 6: receive interrupt enable (rie) bit 6 selects enabling or disabling of the receive data full interrupt request (rxi) and the receive error interrupt request (eri) when receive data is transferred from the receive shift register (rsr) to the receive data register (rdr), and bit rdrf in the serial status register (ssr) is set to 1. there are three kinds of receive error: overrun, framing, and parity. rxi and eri can be released by clearing bit rdrf or the fer, per, or oer error flag to 0, or by clearing bit rie to 0. bit 6 rie description 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled (initial value) 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled bit 5: transmit enable (te) bit 5 selects enabling or disabling of the start of transmit operation. bit 5 te description 0 transmit operation disabled * 1 (txd 32 pin is transmit data pin) (initial value) 1 transmit operation enabled * 2 (txd 32 pin is transmit data pin) notes: 1. bit tdre in ssr is fixed at 1. 2. when transmit data is written to tdr in this state, bit tdr in ssr is cleared to 0 and serial data transmission is started. be sure to carry out serial mode register (smr) settings, and setting of bit spc32 in spcr, to decide the transmission format before setting bit te to 1.
228 bit 4: receive enable (re) bit 4 selects enabling or disabling of the start of receive operation. bit 4 re description 0 receive operation disabled * 1 (rxd pin is i/o port) (initial value) 1 receive operation enabled * 2 (rxd pin is receive data pin) notes: 1. note that the rdrf, fer, per, and oer flags in ssr are not affected when bit re is cleared to 0, and retain their previous state. 2. in this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. be sure to carry out serial mode register (smr) settings to decide the reception format before setting bit re to 1. bit 3: multiprocessor interrupt enable (mpie) bit 3 selects enabling or disabling of the multiprocessor interrupt request. the mpie bit setting is only valid when asynchronous mode is selected and reception is carried out with bit mp in smr set to 1. the mpie bit setting is invalid when bit com is set to 1 or bit mp is cleared to 0. bit 3 mpie description 0 multiprocessor interrupt request disabled (normal receive operation) (initial value) clearing conditions: when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled * note: * receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and oer status flags in ssr is not performed. rxi, eri, and setting of the rdrf, fer, and oer flags in ssr, are disabled until data with the multiprocessor bit set to 1 is received. when a receive character with the multiprocessor bit set to 1 is received, bit mpbr in ssr is set to 1, bit mpie is automatically cleared to 0, and rxi and eri requests (when bits tie and rie in serial control register 3 (scr3) are set to 1) and setting of the rdrf, fer, and oer flags are enabled.
229 bit 2: transmit end interrupt enable (teie) bit 2 selects enabling or disabling of the transmit end interrupt request (tei) if there is no valid transmit data in tdr when msb data is to be sent. bit 2 teie description 0 transmit end interrupt request (tei) disabled (initial value) 1 transmit end interrupt request (tei) enabled * note: * tei can be released by clearing bit tdre to 0 and clearing bit tend to 0 in ssr, or by clearing bit teie to 0. bits 1 and 0: clock enable 1 and 0 (cke1, cke0) bits 1 and 0 select the clock source and enabling or disabling of clock output from the sck 32 pin. the combination of cke1 and cke0 determines whether the sck 32 pin functions as an i/o port, a clock output pin, or a clock input pin. the cke0 bit setting is only valid in case of internal clock operation (cke1 = 0) in asynchronous mode. in synchronous mode, or when external clock operation is used (cke1 = 1), bit cke0 should be cleared to 0. after setting bits cke1 and cke0, set the operating mode in the serial mode register (smr). for details on clock source selection, see table 10.9 in 10.3.1. bit 1 bit 0 description cke1 cke0 communication mode clock source sck 32 pin function 0 0 asynchronous internal clock i/o port * 1 synchronous internal clock serial clock output * 1 0 1 asynchronous internal clock clock output * 2 synchronous reserved 1 0 asynchronous external clock clock input * 3 synchronous external clock serial clock input 1 1 asynchronous reserved synchronous reserved notes: 1. initial value 2. a clock with the same frequency as the bit rate is output. 3. input a clock with a frequency 16 times the bit rate.
230 10.2.7 serial status register (ssr) b it i nitial value r ead/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 oer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r ***** note: * only a write of 0 for flag clearing is possible. ssr is an 8-bit register containing status flags that indicate the operational status of sci3, and multiprocessor bits. ssr can be read or written to by the cpu at any time, but 1 cannot be written to bits tdre, rdrf, oer, per, and fer. bits tend and mpbr are read-only bits, and cannot be modified. ssr is initialized to h'84 upon reset, and in standby, module standby, or watch mode. bit 7: transmit data register empty (tdre) bit 7 indicates that transmit data has been transferred from tdr to tsr. bit 7 tdre description 0 transmit data written in tdr has not been transferred to tsr clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmit data has not been written to tdr, or transmit data written in tdr has been transferred to tsr setting conditions: when bit te in scr3 is cleared to 0 when data is transferred from tdr to tsr (initial value)
231 bit 6: receive data register full (rdrf) bit 6 indicates that received data is stored in rdr. bit 6 rdrf description 0 there is no receive data in rdr (initial value) clearing conditions: after reading rdrf = 1, cleared by writing 0 to rdrf when rdr data is read by an instruction 1 there is receive data in rdr setting conditions: when reception ends normally and receive data is transferred from rsr to rdr note: if an error is detected in the receive data, or if the re bit in scr3 has been cleared to 0, rdr and bit rdrf are not affected and retain their previous state. note that if data reception is completed while bit rdrf is still set to 1, an overrun error (oer) will result and the receive data will be lost. bit 5: overrun error (oer) bit 5 indicates that an overrun error has occurred during reception. bit 5 oer description 0 reception in progress or completed * 1 (initial value) clearing conditions: after reading oer = 1, cleared by writing 0 to oer 1 an overrun error has occurred during reception * 2 setting conditions: when reception is completed with rdrf set to 1 notes: 1. when bit re in scr3 is cleared to 0, bit oer is not affected and retains its previous state. 2. rdr retains the receive data it held before the overrun error occurred, and data received after the error is lost. reception cannot be continued with bit oer set to 1, and in synchronous mode, transmission cannot be continued either.
232 bit 4: framing error (fer) bit 4 indicates that a framing error has occurred during reception in asynchronous mode. bit 4 fer description 0 reception in progress or completed * 1 (initial value) clearing conditions: after reading fer = 1, cleared by writing 0 to fer 1 a framing error has occurred during reception setting conditions: when the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0 * 2 notes: 1. when bit re in scr3 is cleared to 0, bit fer is not affected and retains its previous state. 2. note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. when a framing error occurs the receive data is transferred to rdr but bit rdrf is not set. reception cannot be continued with bit fer set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. bit 3: parity error (per) bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. bit 3 per description 0 reception in progress or completed * 1 (initial value) clearing conditions: after reading per = 1, cleared by writing 0 to per 1 a parity error has occurred during reception * 2 setting conditions: when the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit pm in the serial mode register (smr) notes: 1. when bit re in scr3 is cleared to 0, bit per is not affected and retains its previous state. 2. receive data in which it a parity error has occurred is still transferred to rdr, but bit rdrf is not set. reception cannot be continued with bit per set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1.
233 bit 2: transmit end (tend) bit 2 indicates that bit tdre is set to 1 when the last bit of a transmit character is sent. bit 2 is a read-only bit and cannot be modified. bit 2 tend description 0 transmission in progress clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmission ended (initial value) setting conditions: when bit te in scr3 is cleared to 0 when bit tdre is set to 1 when the last bit of a transmit character is sent bit 1: multiprocessor bit receive (mpbr) bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. bit 1 is a read-only bit and cannot be modified. bit 1 mpbr description 0 data in which the multiprocessor bit is 0 has been received * (initial value) 1 data in which the multiprocessor bit is 1 has been received note: * when bit re is cleared to 0 in scr3 with the multiprocessor format, bit mpbr is not affected and retains its previous state. bit 0: multiprocessor bit transfer (mpbt) bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. the bit mpbt setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting. bit 0 mpbt description 0 a 0 multiprocessor bit is transmitted (initial value) 1 a 1 multiprocessor bit is transmitted
234 10.2.8 bit rate register (brr) b it i nitial value r ead/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w brr is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 of the serial mode register (smr). brr can be read or written by the cpu at any time. brr is initialized to h'ff upon reset, and in standby, module standby, or watch mode. table 10.3 shows examples of brr settings in asynchronous mode. the values shown are for active (high-speed) mode. table 10.3 examples of brr settings for various bit rates (asynchronous mode) (1) osc 32.8 khz 38.4 khz 2 mhz 2.4576 mhz 4 mhz b bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) n n error (%) 110 cannot be used, 221 0.83 150 as error 0 3 0 2 12 0.16 3 3 0 2 25 0.16 200 exceeds 3% 0 2 0 0 155 0.16 3 2 0 250 0 124 0 0 153 0.26 0 249 0 300 0 1 0 0 103 0.16 3 1 0 2 12 0.16 600 0 0 0 0 51 0.16 3 0 0 0 103 0.16 1200 0 25 0.16 2 1 0 0 51 0.16 2400 0 12 0.16 2 0 0 0 25 0.16 4800 0 7 0 0 12 0.16 9600 030 19200 010 31250 000 010 38400 000
235 table 10.3 examples of brr settings for various bit rates (asynchronous mode) (2) osc 10 mhz 16 mhz b bit rate (bit/s) n n error (%) n n error (%) 110 2 88 0.25 2 141 0.02 150 2 64 0.16 2 103 0.16 200 2 48 0.35 2 77 0.16 250 2 38 0.16 2 62 0.79 300 2 51 0.16 600 2 25 0.16 1200 0 129 0.16 0 207 0.16 2400 0 64 0.16 0 103 0.16 4800 0 51 0.16 9600 0 25 0.16 19200 0 12 0.16 31250 0 4 0 0 7 0 38400 notes: 1. the setting should be made so that the error is not more than 1%. 2. the value set in brr is given by the following equation: n = osc 1 (64 2 2n b) where b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.4.) 3. the error in table 10.3 is the value obtained from the following equation, rounded to two decimal places. error (%) = b (rate obtained from n, n, osc) r(bit rate in left-hand column in table 10.3.) 100 r (bit rate in left-hand column in table 10.3.)
236 table 10.4 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. table 10.5 shows the maximum bit rate for each frequency. the values shown are for active (high-speed) mode. table 10.5 maximum bit rate for each frequency (asynchronous mode) maximum bit rate setting osc (mhz) (bit/s) n n 0.0384 * 600 0 0 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 10 156250 0 0 16 250000 0 0 note: * when smr is set up to cks1 = 0, cks0 = 1.
237 table 10.6 shows examples of brr settings in synchronous mode. the values shown are for active (high-speed) mode. table 10.6 examples of brr settings for various bit rates (synchronous mode) (1) osc b bit rate 38.4 khz 2 mhz 4 mhz (bit/s) n n error n n error n n error 200 0 23 0 250 2 124 0 300 2 0 0 500 1k 0 249 0 2.5k 0 99 0 0 199 0 5k 04900990 10k 02400490 25k 0900190 50k 040090 100k 040 250k 000010 500k 0 0 0 1m
238 table 10.6 examples of brr settings for various bit rates (synchronous mode) (2) osc b bit rate 10 mhz 16 mhz (bit/s) n n error n n error 200 250 3 124 0 300 500 2 249 0 1k 2 124 0 2.5k 2490 5k 0 249 0 2 24 0 10k 0 124 0 0 199 0 25k 0490 0790 50k 0240 0390 100k 0190 250k 0 4 0 0 7 0 500k 030 1m 010 blank: cannot be set. : a setting can be made, but an error will result. notes: the value set in brr is given by the following equation: n = osc 1 (8 2 2n b) where b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.7.)
239 table 10.7 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 10.2.9 clock stop register 1 (ckstpr1) tfckstp tackstp s32ckstp adckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bits relating to sci3 are described here. for details of the other bits, see the sections on the relevant modules. bit 5: sci3 module standby mode control (s32ckstp) bit 5 controls setting and clearing of module standby mode for sci3. s32ckstp description 0 sci3 is set to module standby mode 1 sci3 module standby mode is cleared (initial value) note: all sci3 register is initialized in module standby mode.
240 10.2.10 serial port control register (spcr) b it i nitial value r ead/write 7 1 6 1 5 spc32 0 r/w 4 w 3 scinv3 0 r/w 0 w 2 scinv2 0 r/w 1 w spcr is an 8-bit readable/writable register that performs rxd 32 and txd 32 pin input/output data inversion switching. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bits 4, 1, and 0: reserved bits bits 4, 1, and 0 are reserved; only 0 can be written to these bits. bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0 txd 32 output data is not inverted (initial value) 1 txd 32 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted.
241 bit 2 scinv2 description 0 rxd 32 input data is not inverted (initial value) 1 rxd 32 input data is inverted 10.3 operation 10.3.1 overview sci3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. the serial mode register (smr) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8. the clock source for sci3 is determined by bit com in smr and bits cke1 and cke0 in scr3, as shown in table 10.9. 1. asynchronous mode ? ? ? ? ? ? ?
242 table 10.8 smr settings and corresponding data transfer formats smr data transfer format bit 7 com bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multiprocessor bit parity bit stop bit length 0 0 0 0 0 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 0 1 0 0 8-bit data yes no 1 bit 1 2 bits 1 0 5-bit data no 1 bit 1 2 bits 1 0 0 7-bit data yes 1 bit 1 2 bits 1 0 5-bit data no yes 1 bit 1 2 bits 1 * 0 ** synchronous mode 8-bit data no no no * : don t care
243 table 10.9 smr and scr3 settings and clock source selection smr scr3 bit 7 bit 1 bit 0 transmit/receive clock com cke1 cke0 mode clock source sck 32 pin function 0 0 0 asynchronous internal i/o port (sck 32 pin not used) 1 mode outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency 16 times bit rate 1 0 0 synchronous internal outputs serial clock 1 0 mode external inputs serial clock 0 1 1 reserved (do not specify these combinations) 10 1 11 1 3. interrupts and continuous transmission/reception sci3 can carry out continuous reception using rxi and continuous transmission using txi. these interrupts are shown in table 10.10. table 10.10 transmit/receive interrupts interrupt flags interrupt request conditions notes rxi rdrf rie when serial reception is performed normally and receive data is transferred from rsr to rdr, bit rdrf is set to 1, and if bit rie is set to 1 at this time, rxi is enabled and an interrupt is requested. (see figure 10.2 (a).) the rxi interrupt routine reads the receive data transferred to rdr and clears bit rdrf to 0. continuous reception can be performed by repeating the above operations until reception of the next rsr data is completed. txi tdre tie when tsr is found to be empty (on completion of the previous transmission) and the transmit data placed in tdr is transferred to tsr, bit tdre is set to 1. if bit tie is set to 1 at this time, txi is enabled and an interrupt is requested. (see figure 10.2 (b).) the txi interrupt routine writes the next transmit data to tdr and clears bit tdre to 0. continuous transmission can be performed by repeating the above operations until the data transferred to tsr has been transmitted. tei tend teie when the last bit of the character in tsr is transmitted, if bit tdre is set to 1, bit tend is set to 1. if bit teie is set to 1 at this time, tei is enabled and an interrupt is requested. (see figure 10.2 (c).) tei indicates that the next transmit data has not been written to tdr when the last bit of the transmit character in tsr is sent.
244 rdr rsr (reception in progress) rdrf = 0 rxd 32 pin rdr rsr (reception completed, transfer) rdrf 1 (rxi request when rie = 1) rxd 32 pin figure 10.2 (a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmission in progress) tdre = 0 txd 32 pin tdr tsr (transmission completed, transfer) tdre 1 (txi request when tie = 1) txd 32 pin figure 10.2 (b) tdre setting and txi interrupt tdr tsr (transmission in progress) tend = 0 txd 32 pin tdr tsr (reception completed) tend 1 (tei request when teie = 1) txd 32 pin figure 10.2 (c) tend setting and tei interrupt
245 10.3.2 operation in asynchronous mode in asynchronous mode, serial communication is performed with synchronization provided character by character. a start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. sci3 has separate transmission and reception units, allowing full-duplex communication. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.3. serial data start bit 1 bit transmit/receive data parity bit stop bit(s) 5, 7 or 8 bits one transfer data unit (character or frame) 1 bit or none 1 or 2 bits mark state 1 (msb) (lsb) figure 10.3 data format in asynchronous communication in asynchronous communication, the communication line is normally in the mark state (high level). sci3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. one transfer data character consists of a start bit (low level), followed by transmit/receive data (lsb-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. the data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
246 table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. the format is selected by the settings in the serial mode register (smr). table 10.11 data transfer formats (asynchronous mode) 1 chr 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 pe mp stop 2 3 4 5 8-bit data serial data transfer format and frame length smr stop s 6 7 8 9 10 11 12 8-bit data s 7-bit data stop stop s stop 7-bit data s stop stop 5-bit data s stop 5-bit data s stop stop 8-bit data p s stop 8-bit data p s stop stop 8-bit data mpb s stop 8-bit data mpb s stop stop 7-bit data p stop s stop 7-bit data stop s 5-bit data stop p p p s 5-bit data stop stop s notation: s: stop: p: mpb: start bit stop bit parity bit multiprocessor bit stop 7-bit data stop s 7-bit data stop mpb mpb s
247 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 32 pin can be selected as the sci3 transmit/receive clock. the selection is made by means of bit com in smr and bits sce1 and cke0 in scr3. see table 10.9 for details on clock source selection. when an external clock is input at the sck 32 pin, the clock frequency should be 16 times the bit rate. when sci3 operates on an internal clock, the clock can be output at the sck 32 pin. in this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10.4. 1 character (1 frame) 0 d0d1d2d3d4d5d6d70/1 1 1 clock serial data figure 10.4 phase relationship between output clock and transfer data (asynchronous mode) (8-bit data, parity, 2 stop bits) 3. data transfer operations sci3 initialization before data is transferred on sci3, bits te and re in scr3 must first be cleared to 0, and then sci3 must be initialized as follows. note: if the operation mode or data transfer format is changed, bits te and re must first be cleared to 0. when bit te is cleared to 0, bit tdre is set to 1. note that the rdrf, per, fer, and oer flags and the contents of rdr are retained when re is cleared to 0. when an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. when an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization.
248 figure 10.5 shows an example of a flowchart for initializing sci3. start end clear bits te and re to 0 in scr3 1 2 3 set bits cke1 and cke0 set data transfer format in smr set bit spc32 to 1 in spcr set value in brr no wait yes 4 set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in scr3 has 1-bit period elapsed? set clock selection in scr3. be sure to clear the other bits to 0. if clock output is selected in asynchronous mode, the clock is output immediately after setting bits cke1 and cke0. if clock output is selected for reception in synchronous mode, the clock is output immediately after bits cke1, cke0, and re are set to 1. set the data transfer format in the serial mode register (smr). write the value corresponding to the transfer rate in brr. this operation is not necessary when an external clock is selected. wait for at least one bit period, then set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in pmr7. setting bits te and re enables the txd 32 and rxd 32 pins to be used. in asynchronous mode the mark state is established when transmitting, and the idle state waiting for a start bit when receiving. 1. 2. 3. 4. figure 10.5 example of sci3 initialization flowchart
249 transmitting figure 10.6 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 2 3 write transmit data to tdr read bit tend in ssr set pdr = 0, pcr = 1 clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? no yes yes yes no break output? read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. (after the te bit is set to 1, one frame of 1s is output, then transmission is possible.) when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.6 example of data transmission flowchart (asynchronous mode)
250 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd 32 pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1, bit tend in ssr bit is set to 1the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.7 shows an example of the operation when transmitting in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.7 example of operation when transmitting in asynchronous mode (8-bit data, parity, 1 stop bit)
251 receiving figure 10.8 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bits oer, per, fer in ssr 1 2 3 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + per + fer = 1? no rdrf = 1? yes continue data reception? no no yes receive error processing (a) read bits oer, per, and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the stop bit of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. 1. 2. 3. figure 10.8 example of data reception flowchart (asynchronous mode)
252 start receive error processing end of receive error processing 4 clear bits oer, per, fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? yes per = 1? no no no no overrun error processing framing error processing (a) parity error processing if a receive error has occurred, read bits oer, per, and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer, per, and fer are all cleared to 0. reception cannot be resumed if any of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 32 pin. 4. figure 10.8 example of data reception flowchart (asynchronous mode) (cont)
253 sci3 operates as follows when receiving data. sci3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. reception is carried out in accordance with the relevant data transfer format in table 10.11. the received data is first placed in rsr in lsb-to-msb order, and then the parity bit and stop bit(s) are received. sci3 then carries out the following checks. ? ? ? table 10.12 receive error detection conditions and receive data processing receive error abbreviation detection conditions receive data processing overrun error oer when the next date receive operation is completed while bit rdrf is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the parity (odd or even) set in smr is different from that of the received data receive data is transferred from rsr to rdr
254 figure 10.9 shows an example of the operation when receiving in asynchronous mode. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 start bit detected eri request in response to framing error figure 10.9 example of operation when receiving in asynchronous mode (8-bit data, parity, 1 stop bit) 10.3.3 operation in synchronous mode in synchronous mode, sci3 transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. sci3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception.
255 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.10. serial clock serial data note: * high level except in continuous transmission/reception lsb msb * * bit 1 bit 0 bit 2 bit 3 bit 4 8 bits one transfer data unit (character or frame) bit 5 bit 6 bit 7 don't care don't care figure 10.10 data format in synchronous communication in synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. data confirmation is guaranteed at the rising edge of the serial clock. one transfer data character begins with the lsb and ends with the msb. after output of the msb, the communication line retains the msb state. when receiving in synchronous mode, sci3 latches receive data at the rising edge of the serial clock. the data transfer format uses a fixed 8-bit data length. parity and multiprocessor bits cannot be added. 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 32 pin can be selected as the sci3 serial clock. the selection is made by means of bit com in smr and bits cke1 and cke0 in scr3. see table 10.9 for details on clock source selection. when sci3 operates on an internal clock, the serial clock is output at the sck 32 pin. eight pulses of the serial clock are output in transmission or reception of one character, and when sci3 is not transmitting or receiving, the clock is fixed at the high level.
256 3. data transfer operations sci3 initialization data transfer on sci3 first of all requires that sci3 be initialized as described in 10.3.2 3. sci3 initialization, and shown in figure 10.5. transmitting figure 10.11 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 2 write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? yes yes no read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically, the clock is output, and data transmission is started. when clock output is selected, the clock is output and data transmission started when data is written to tdr. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. 1. 2. figure 10.11 example of data transmission flowchart (synchronous mode)
257 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. when clock output mode is selected, sci3 outputs 8 serial clock pulses. when an external clock is selected, data is output in synchronization with the input clock. serial data is transmitted from the txd32 pin in order from the lsb (bit 0) to the msb (bit 7). when the msb (bit 7) is sent, checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and starts transmission of the next frame. if bit tdre is set to 1, sci3 sets bit tend to 1 in ssr, and after sending the msb (bit 7), retains the msb state. if bit teie in scr3 is set to 1 at this time, a tei request is made. after transmission ends, the sck pin is fixed at the high level. note: transmission is not possible if an error flag (oer, fer, or per) that indicates the data reception status is set to 1. check that these error flags are all cleared to 0 before a transmit operation. figure 10.12 shows an example of the operation when transmitting in synchronous mode. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi request data written to tdr tdre cleared to 0 txi request tei request figure 10.12 example of operation when transmitting in synchronous mode
258 receiving figure 10.13 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bit oer in ssr 1 2 3 4 read bit rdrf in ssr overrun error processing 4 clear bit oer to 0 in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer = 1? no rdrf = 1? yes continue data reception? no no yes overrun error processing end of overrun error processing start overrun error processing read bit oer in the serial status register (ssr) to determine if there is an error. if an overrun error has occurred, execute overrun error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. reception cannot be resumed if bit oer is set to 1. 1. 2. 3. 4. figure 10.13 example of data reception flowchart (synchronous mode)
259 sci3 operates as follows when receiving data. sci3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. the received data is placed in rsr in lsb-to-msb order. after the data has been received, sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. if this check shows that there is no overrun error, bit rdrf is set to 1, and the receive data is stored in rdr. if bit rie is set to 1 in scr3, an rxi interrupt is requested. if the check identifies an overrun error, bit oer is set to 1. bit rdrf remains set to 1. if bit rie is set to 1 in scr3, an eri interrupt is requested. see table 10.12 for the conditions for detecting a receive error, and receive data processing. note: no further receive operations are possible while a receive error flag is set. bits oer, fer, per, and rdrf must therefore be cleared to 0 before resuming reception. figure 10.14 shows an example of the operation when receiving in synchronous mode. serial clock serial data bit 0 bit 7 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi request rdr data read rdre cleared to 0 rxi request eri request in response to overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 10.14 example of operation when receiving in synchronous mode
260 simultaneous transmit/receive figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. this procedure should be followed for simultaneous transmission/reception after initializing sci3. start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 2 3 4 write transmit data to tdr read bit oer in ssr read bit rdrf in ssr clear bits te and re to 0 in scr3 yes tdre = 1? no oer = 1? no rdrf = 1? yes continue data transmission/reception? no yes no read receive data in rdr yes overrun error processing read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data transmission/reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. before receiving the msb (bit 7) of the current frame, also read tdre = 1 to confirm that a write can be performed, then write data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically, and when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. transmis- sion and reception cannot be resumed if bit oer is set to 1. see figure 10-13 for details on overrun error processing. 1. 2. 3. 4. figure 10.15 example of simultaneous data transmission/reception flowchart (synchronous mode)
261 notes: 1. when switching from transmission to simultaneous transmission/reception, check that sci3 has finished transmitting and that bits tdre and tend are set to 1, clear bit te to 0, and then set bits te and re to 1 simultaneously. 2. when switching from reception to simultaneous transmission/reception, check that sci3 has finished receiving, clear bit re to 0, then check that bit rdrf and the error flags (oer, fer, and per) are cleared to 0, and finally set bits te and re to 1 simultaneously. 10.3.4 multiprocessor communication function the multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). in multiprocessor communication, each receiver is assigned its own id code. the serial communication cycle consists of two cycles, an id transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. these two cycles are differentiated by means of the multiprocessor bit, 1 indicating an id transmission cycle, and 0, a data transmission cycle. the sender first sends transfer data with a 1 multiprocessor bit added to the id code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. when a receiver receives transfer data with the multiprocessor bit set to 1, it compares the id code with its own id code, and if they are the same, receives the transfer data sent next. if the id codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. in this way, a number of processors can exchange data among themselves. figure 10.16 shows an example of communication between processors using the multiprocessor format.
262 sender serial data receiver a (id = 01) (id = 02) receiver b h'01 id transmission cycle (specifying the receiver) data transmission cycle (sending data to the receiver specified by the id) mpb: multiprocessor bit (mpb = 1) (mpb = 0) h'aa communication line (id = 03) receiver c (id = 04) receiver d figure 10.16 example of inter-processor communication using multiprocessor format (sending data h'aa to receiver a) there is a choice of four data transfer formats. if a multiprocessor format is specified, the parity bit specification is invalid. see table 10.11 for details. for details on the clock used in multiprocessor communication, see 10.3.2, operation in synchronous mode. multiprocessor transmitting figure 10.17 shows an example of a flowchart for multiprocessor data transmission. this procedure should be followed for multiprocessor data transmission after initializing sci3.
263 start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 3 2 set bit mpdt in ssr write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 set pdr = 0, pcr = 1 yes tdre = 1? no continue data transmission? no tend = 1? break output? no yes yes no yes read the serial status register (ssr) and check that bit tdre is set to 1, then set bit mpbt in ssr to 0 or 1 and write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.17 example of multiprocessor data transmission flowchart
264 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1 bit tend in ssr bit is set to 1, the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.18 shows an example of the operation when transmitting using the multiprocessor format. 1 frame start bit start bit transmit data transmit data mpb mpb stop bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.18 example of operation when transmitting using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) multiprocessor receiving figure 10.19 shows an example of a flowchart for multiprocessor data reception. this procedure should be followed for multiprocessor data reception after initializing sci3.
265 start end read bits oer and fer in ssr 2 set bit mpie to 1 in scr3 1 3 4 5 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + fer = 1? no rdrf = 1? yes continue data reception? no no yes read bits oer and fer in ssr no own id? yes read bit rdrf in ssr yes oer + fer = 1? no read receive data in rdr no rdrf = 1? yes receive error processing (a) set bit mpie to 1 in scr3. read bits oer and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr and compare it with this receiver's own id. if the id is not this receiver's, set bit mpie to 1 again. when the rdr data is read, bit rdrf is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1, then read the data in rdr. if a receive error has occurred, read bits oer and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer and fer are both cleared to 0. reception cannot be resumed if either of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 32 pin. 1. 2. 3. 4. 5. figure 10.19 example of multiprocessor data reception flowchart
266 start receive error processing end of receive error processing clear bits oer and fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? no no no overrun error processing framing error processing (a) figure 10.19 example of multiprocessor data reception flowchart (cont) figure 10.20 shows an example of the operation when receiving using the multiprocessor format.
267 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 no rxi request rdr retains previous state rdr data read when data is not this receiver's id, bit mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 rxi request rdrf cleared to 0 rdr data read when data is this receiver's id, reception is continued rdr data read bit mpie set to 1 again figure 10.20 example of operation when receiving using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit)
268 10.4 interrupts sci3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). these interrupts have the same vector address. the various interrupt requests are shown in table 10.13. table 10.13 sci3 interrupt requests interrupt abbreviation interrupt request vector address rxi interrupt request initiated by receive data full flag (rdrf) h'0024 txi interrupt request initiated by transmit data empty flag (tdre) tei interrupt request initiated by transmit end flag (tend) eri interrupt request initiated by receive error flag (oer, fer, per) each interrupt request can be enabled or disabled by means of bits tie and rie in scr3. when bit tdre is set to 1 in ssr, a txi interrupt is requested. when bit tend is set to 1 in ssr, a tei interrupt is requested. these two interrupts are generated during transmission. the initial value of bit tdre in ssr is 1. therefore, if the transmit data empty interrupt request (txi) is enabled by setting bit tie to 1 in scr3 before transmit data is transferred to tdr, a txi interrupt will be requested even if the transmit data is not ready. also, the initial value of bit tend in ssr is 1. therefore, if the transmit end interrupt request (tei) is enabled by setting bit teie to 1 in scr3 before transmit data is transferred to tdr, a tei interrupt will be requested even if the transmit data has not been sent. effective use of these interrupt requests can be made by having processing that transfers transmit data to tdr carried out in the interrupt service routine. to prevent the generation of these interrupt requests (txi and tei), on the other hand, the enable bits for these interrupt requests (bits tie and teie) should be set to 1 after transmit data has been transferred to tdr. when bit rdrf is set to 1 in ssr, an rxi interrupt is requested, and if any of bits oer, per, and fer is set to 1, an eri interrupt is requested. these two interrupt requests are generated during reception. for further details, see 3.3, interrupts.
269 10.5 application notes the following points should be noted when using sci3. 1. relation between writes to tdr and bit tdre bit tdre in the serial status register (ssr) is a status flag that indicates that data for serial transmission has not been prepared in tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. when sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr irrespective of the state of bit tdre, but if new data is written to tdr while bit tdre is cleared to 0, the data previously stored in tdr will be lost of it has not yet been transferred to tsr. accordingly, to ensure that serial transmission is performed dependably, you should first check that bit tdre is set to 1, then write the transmit data to tdr once only (not two or more times). 2. operation when a number of receive errors occur simultaneously if a number of receive errors are detected simultaneously, the status flags in ssr will be set to the states shown in table 10.14. if an overrun error is detected, data transfer from rsr to rdr will not be performed, and the receive data will be lost. table 10.14 ssr status flag states and receive data transfer ssr status flags receive data transfer rdrf * oer fer per rsr rdr receive error status 1 1 0 0 x overrun error 0 0 1 0 o framing error 0 0 0 1 o parity error 1 1 1 0 x overrun error + framing error 1 1 0 1 x overrun error + parity error 0 0 1 1 o framing error + parity error 1 1 1 1 x overrun error + framing error + parity error o : receive data is transferred from rsr to rdr. x : receive data is not transferred from rsr to rdr. note: * bit rdrf retains its state prior to data reception. however, note that if rdr is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, rdrf will be cleared to 0.
270 3. break detection and processing when a framing error is detected, a break can be detected by reading the value of the rxd 32 pin directly. in a break, the input from the rxd 32 pin becomes all 0s, with the result that bit fer is set and bit per may also be set. sci3 continues the receive operation even after receiving a break. note, therefore, that even though bit fer is cleared to 0 it will be set to 1 again. 4. mark state and break detection when bit te is cleared to 0, the txd 32 pin functions as an i/o port whose input/output direction and level are determined by pdr and pcr. this fact can be used to set the txd 32 pin to the mark state, or to detect a break during transmission. to keep the communication line in the mark state (1 state) until bit te is set to 1, set pcr = 1 and pdr = 1. since bit te is cleared to 0 at this time, the txd 32 pin functions as an i/o port and 1 is output. to detect a break, clear bit te to 0 after setting pcr = 1 and pdr = 0. when bit te is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the txd 32 pin functions as an i/o port, and 0 is output from the txd 32 pin. 5. receive error flags and transmit operation (synchronous mode only) when a receive error flag (oer, per, or fer) is set to 1, transmission cannot be started even if bit tdre is cleared to 0. the receive error flags must be cleared to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if bit re is cleared to 0. 6. receive data sampling timing and receive margin in asynchronous mode in asynchronous mode, sci3 operates on a basic clock with a frequency 16 times the transfer rate. when receiving, sci3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. receive data is latched internally at the 8th rising edge of the basic clock. this is illustrated in figure 10.21.
271 0 7 15 0 7 15 0 internal basic clock receive data (rxd32) start bit d0 16 clock pulses 8 clock pulses d1 synchronization sampling timing data sampling timing figure 10.21 receive data sampling timing in asynchronous mode consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). m ={(0.5 1 ) d 0.5 (l 0.5) f} 1/(2
272 7. relation between rdr reads and bit rdrf in a receive operation, sci3 continually checks the rdrf flag. if bit rdrf is cleared to 0 when reception of one frame ends, normal data reception is completed. if bit rdrf is set to 1, this indicates that an overrun error has occurred. when the contents of rdr are read, bit rdrf is cleared to 0 automatically. therefore, if bit rdr is read more than once, the second and subsequent read operations will be performed while bit rdrf is cleared to 0. note that, when an rdr read is performed while bit rdrf is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. this is illustrated in figure 10.22. communication line rdrf rdr frame 1 frame 2 frame 3 data 1 data 1 rdr read rdr read data 1 is read at point (a) data 2 data 3 data 2 (a) data 2 is read at point (b) (b) figure 10.22 relation between rdr read timing and data in this case, only a single rdr read operation (not two or more) should be performed after first checking that bit rdrf is set to 1. if two or more reads are performed, the data read the first time should be transferred to ram, etc., and the ram contents used. also, ensure that there is sufficient margin in an rdr read operation before reception of the next frame is completed. to be precise in terms of timing, the rdr read should be completed before bit 7 is transferred in synchronous mode, or before the stop bit is transferred in asynchronous mode. 8. transmit and receive operations when making a state transition make sure that transmit and receive operations have completely finished before carrying out state transition processing.
273 9. switching sck 32 function if pin sck 32 is used as a clock output pin by sci3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. a. when an sck 32 function is switched from clock output to non clock-output when stopping data transfer, issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. in this case, bit com in smr should be left 1. the above prevents sck 32 from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to sck 32 , the line connected to sck 32 should be pulled up to the v cc level via a resistor, or supplied with output from an external device. b. when an sck 32 function is switched from clock output to general input/output when stopping data transfer, (i) issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. (ii) clear bit com in smr to 0 (iii) clear bits cke1 and cke0 in scr3 to 0 note that special care is also needed here to avoid an intermediate level of voltage from being applied to sck 32 . 10. set up at subactive or subsleep mode at subactive or subsleep mode, sci3 becomes possible use only at cpu clock is w/2.
274
275 section 11 10-bit pwm 11.1 overview the h8/3802 series is provided with two on-chip 10-bit pwms (pulse width modulators), designated pwm1 and pwm2, with identical functions. the pwms can be used as d/a converters by connecting a low-pass filter. in this section the suffix m (m = 1 or 2) is used with register names, etc., as in pwdrlm, which denotes the pwdrl registers for each pwm. 11.1.1 features features of the 10-bit pwms are as follows. ? choice of four conversion periods any of the following conversion periods can be chosen: 4,096/? with a minimum modulation width of 4/ 2,048/? with a minimum modulation width of 2/ 1,024/? with a minimum modulation width of 1/ 512/? with a minimum modulation width of 1/2 ? pulse division method for less ripple ? use of module standby mode enables this module to be placed in standby mode independently when not used.
276 11.1.2 block diagram figure 11.1 shows a block diagram of the 10-bit pwm. internal data bus pwdrlm pwdrum pwcrm pwm waveform generator ?2 ?4 ?8 n otation: p wdrlm: p wdrum: p wcrm: pwm data register l pwm data register u pwm control register m= 1 or 2 pwmm figure 11.1 block diagram of the 10 bit pwm 11.1.3 pin configuration table 11.1 shows the output pin assigned to the 10-bit pwm. table 11.1 pin configuration name abbrev. i/o function pwm1 output pin pwm1 output pulse-division pwm waveform output (pwm1) pwm2 output pin pwm2 output pulse-division pwm waveform output (pwm2)
277 11.1.4 register configuration table 11.2 shows the register configuration of the 10-bit pwm. table 11.2 register configuration name abbrev. r/w initial value address pwm1 control register pwcr1 w h'fc h'ffd0 pwm1 data register u pwdru1 w h'fc h'ffd1 pwm1 data register l pwdrl1 w h'00 h'ffd2 pwm2 control register pwcr2 w h'fc h'ffcd pwm2 data register u pwdru2 w h'fc h'ffce pwm2 data register l pwdrl2 w h'00 h'ffcf clock stop register 2 ckstpr2 r/w h'ff h'fffb
278 11.2 register descriptions 11.2.1 pwm control register (pwcrm) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcrm0 0 w 2 1 1 pwcrm1 0 w pwcrm is an 8-bit write-only register for input clock selection. upon reset, pwcrm is initialized to h'fc. bits 7 to 2: reserved bits bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. bits 1 and 0: clock select 1 and 0 (pwcrm1, pwcrm0) bits 1 and 0 select the clock supplied to the 10-bit pwm. these bits are write-only bits; they are always read as 1. bit 1 pwcrm1 bit 0 pwcrm0 description 0 0 the input clock is (t * = 1/ ) (initial value) the conversion period is 512/ , with a minimum modulation width of 1/2 0 1 the input clock is /2 (t * = 2/ ) the conversion period is 1,024/ , with a minimum modulation width of 1/ 1 0 the input clock is /4 (t * = 4/ ) the conversion period is 2,048/ , with a minimum modulation width of 2/ 1 1 the input clock is /8 (t * = 8/ ) the conversion period is 4,096/ , with a minimum modulation width of 4/ note: * period of pwm input clock.
279 11.2.2 pwm data registers u and l (pwdrum, pwdrlm) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwdrum 0 0 w 2 1 1 pwdrum 1 0 w pwdrum bit initial value read/write 7 pwdrlm 7 0 w 6 pwdrlm 6 0 w 5 pwdrlm 5 0 w 4 pwdrlm 4 0 w 3 pwdrlm 3 0 w 0 pwdrlm 0 0 w 2 pwdrlm 2 0 w 1 pwdrlm 1 0 w pwdrlm pwdrum and pwdrlm form a 10-bit write-only register, with the upper 2 bits assigned to pwdrum and the lower 8 bits to pwdrlm. the value written to pwdrum and pwdrlm gives the total high-level width of one pwm waveform cycle. when 10-bit data is written to pwdrum and pwdrlm, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 10-bit data should always be written in the following sequence: 1. write the lower 8 bits to pwdrlm. 2. write the upper 2 bits to pwdrum for the same channel. pwdrum and pwdrlm are write-only registers. if they are read, all bits are read as 1. upon reset, pwdrum is initialized to h'fc, and pwdrlm to h'00. 11.2.3 clock stop register 2 (ckstpr2) pw1ckstp ldckstp pw2ckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the pwm is described here. for details of the other bits, see the sections on the relevant modules.
280 bits 4 and 1: pwm module standby mode control (pwmckstp) bits 4 and 1 control setting and clearing of module standby mode for the pwmm. pwmckstp description 0 pwmm is set to module standby mode 1 pwmm module standby mode is cleared (initial value)
281 11.3 operation 11.3.1 operation when using the 10-bit pwm, set the registers in the following sequence. 1. set pwm1 or pwm2 in pmr9 to 1 for the pwm channel to be used, so that pin p9 0 /pwm1 or p9 1 /pwm2 is designated as the pwm output pin. 2. set bits pwcrm1 and pwcrm0 in the pwm control register (pwcrm) to select a conversion period of 4,096/?(pwcrm1 = 1, pwcrm0 = 1), 2,048/?(pwcrm1 = 1, pwcrm0 = 0), 1,024/?(pwcrm1 = 0, pwcrm0 = 1), or 512/?(pwcrm1 = 0, pwcrm0 = 0). 3. set the output waveform data in pwdrum and pwdrlm. be sure to write in the correct sequence, first pwdrlm then pwdrum for the same channel. when data is written to pwdrum, the data will be latched in the pwm waveform generator, updating the pwm waveform generation in synchronization with internal signals. one conversion period consists of 4 pulses, as shown in figure 11.2. the total of the high-level pulse widths during this period (t h ) corresponds to the data in pwdrum and pwdrlm. this relation can be represented as follows. t h = (data value in pwdrum and pwdrlm + 4) t /2 where t?is the pwm input clock period: 1/?(pwcrm = h'0), 2/?(pwcrm = h'1), 4/?(pwcrm = h'2), or 8/?(pwcrm = h'3). example: settings in order to obtain a conversion period of 1,024 ?: when pwcrm1 = 0 and pwcrm0 = 0, the conversion period is 512/? so ?must be 0.5 mhz. in this case, tfn = 256 ?, with 1/2?(resolution) = 1.0 ?. when pwcrm1 = 0 and pwcrm0 = 1, the conversion period is 1,024/? so ?must be 1 mhz. in this case, tfn = 256 ?, with 1/?(resolution) = 1.0 ?. when pwcrm1 = 1 and pwcrm0 = 0, the conversion period is 2,048/?, so ?must be 2 mhz. in this case, tfn = 256 ?, with 2/?(resolution) = 1.0 ?. when pwcrm1 = 1 and pwcrm0 = 1, the conversion period is 4,096/? so ?must be 4 mhz. in this case, t fn = 256 ?, with 4/?(resolution) = 1.0 ? accordingly, for a conversion period of 1,024 ?, the system clock frequency (? must be 0.5 mhz, 1 mhz, 2 mhz, or 4mhz.
282 1 conversion period t f1 t h1 t h2 t h3 t h4 t f2 t f3 t f4 t h = t h1 +t h2 +t h3 +t h4 t f1 = t f2 = t f3 =t f4 figure 11.2 pwm output waveform 11.3.2 pwm operation modes pwm operation modes are shown in table 11.3. table 11.3 pwm operation modes operation mode reset active sleep watch subactive subsleep standby module standby pwcrm reset functions functions held held held held held pwdrum reset functions functions held held held held held pwdrlm reset functions functions held held held held held
283 section 12 a/d converter 12.1 overview the h8/3802 series includes on-chip a resistance-ladder-based successive-approximation analog- to-digital converter, and can convert up to 4 channels of analog input. 12.1.1 features the a/d converter has the following features. ? 10-bit resolution ? four input channels ? conversion time: approx. 12.4 ? per channel (at 5 mhz operation) ? built-in sample-and-hold function ? interrupt requested on completion of a/d conversion ? use of module standby mode enables this module to be placed in standby mode independently when not used.
284 12.1.2 block diagram figure 12.1 shows a block diagram of the a/d converter. internal data bus amr adsr adrrh adrrl control logic + com- parator an an an an av av cc ss multiplexer reference voltage irrad av cc av ss 0 1 2 3 notation: amr: adsr: adrr: irrad: a/d mode register a/d start register a/d result register a/d conversion end interrupt request flag figure 12.1 block diagram of the a/d converter
285 12.1.3 pin configuration table 12.1 shows the a/d converter pin configuration. table 12.1 pin configuration name abbrev. i/o function analog power supply av cc input power supply and reference voltage of analog part analog ground av ss input ground and reference voltage of analog part analog input 0 an 0 input analog input channel 0 analog input 1 an 1 input analog input channel 1 analog input 2 an 2 input analog input channel 2 analog input 3 an 3 input analog input channel 3 12.1.4 register configuration table 12.2 shows the a/d converter register configuration. table 12.2 register configuration name abbrev. r/w initial value address a/d mode register amr r/w h'30 h'ffc6 a/d start register adsr r/w h'7f h'ffc7 a/d result register h adrrh r not fixed h'ffc4 a/d result register l adrrl r not fixed h'ffc5 clock stop register 1 ckstpr1 r/w h'ff h'fffa
286 12.2 register descriptions 12.2.1 a/d result registers (adrrh, adrrl) bit 7 6 5 4 3 adrrh adrrl 0 21 76543 0 21 initial value read/write not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r adr9 adr8 adr7 adr6 adr5 adr2 adr4 adr3 adr1 adr0 adrrh and adrrl together comprise a 16-bit read-only register for holding the results of analog-to-digital conversion. the upper 8 bits of the data are held in adrrh, and the lower 2 bits in adrrl. adrrh and adrrl can be read by the cpu at any time, but the adrrh and adrrl values during a/d conversion are not fixed. after a/d conversion is complete, the conversion result is stored as 10-bit data, and this data is held until the next conversion operation starts. adrrh and adrrl are not cleared on reset. 12.2.2 a/d mode register (amr) bit initial value read/write 7 cks 0 r/w 6 0 r/w 5 1 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'30.
287 bit 7: clock select (cks) bit 7 sets the a/d conversion speed. bit 7 conversion time cks conversion period ?= 1 mhz ?= 5 mhz 0 62/ (initial value) 62 s 12.4 s 1 31/ 31 s * note: * operation is not guaranteed if the conversion time is less than 12.4 s. set bit 7 for a value of at least 12.4 s. bit 6: reserved bit bit 6 is reserved; only 0 can be written to this bit. bits 5 and 4: reserved bits bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. bits 3 to 0: channel select (ch3 to ch0) bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0. bit 3 ch3 bit 2 ch2 bit 1 ch1 bit 0 ch0 analog input channel 00 ** no channel selected (initial value) 0100an 0 0101an 1 0110an 2 0111an 3 1 0 0 0 setting prohibited 1001 1010 1011 *: don t care
288 12.2.3 a/d start register (adsr) bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf), which also sets adsf to 1. when conversion is complete, the converted data is set in adrrh and adrrl, and at the same time adsf is cleared to 0. bit 7: a/d start flag (adsf) bit 7 controls and indicates the start and end of a/d conversion. bit 7 adsf description 0 read: indicates the completion of a/d conversion (initial value) write: stops a/d conversion 1 read: indicates a/d conversion in progress write: starts a/d conversion bits 6 to 0: reserved bits bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
289 12.2.4 clock stop register 1 (ckstpr1) tfckstp tackstp s32ckstp adckstp 76543210 1 1111111 r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the a/d converter is described here. for details of the other bits, see the sections on the relevant modules. bit 4: a/d converter module standby mode control (adckstp) bit 4 controls setting and clearing of module standby mode for the a/d converter. adckstp description 0 a/d converter is set to module standby mode 1 a/d converter module standby mode is cleared (initial value)
290 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 10- bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 a/d converter operation modes a/d converter operation modes are shown in table 12.3. table 12.3 a/d converter operation modes operation mode reset active sleep watch subactive subsleep standby module standby amr reset functions functions held held held held held adsr reset functions functions held held held held held adrrh held * functions functions held held held held held adrrl held * functions functions held held held held held note: * undefined in a power-on reset.
291 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see 3.3, interrupts. 12.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12.2 shows the operation timing. 1. bits ch3 to ch0 of the a/d mode register (amr) are set to 0101, making pin an 1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion result is stored is stored in adrrh and adrrl. at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. figures 12.3 and 12.4 show flow charts of procedures for using the a/d converter.
292 idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 1 (an 1 ) operation state adrrh adrrl set * set * set * read conversion result read conversion result a/d conversion result (1) a/d conversion result (2) a/d conversion starts note: ( ) indicates instruction execution by software. * figure 12.2 typical a/d converter operation timing
293 start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrrh/adrrl data figure 12.3 flow chart of procedure for using a/d converter (polling by software)
294 start set a/d conversion speed and input channels enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no end yes no clear bit irrad to 0 in irr2 read adrrh/adrrl data perform a/d conversion? figure 12.4 flow chart of procedure for using a/d converter (interrupts used) 12.6 application notes ? data in adrrh and adrrl should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. ? changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. ? when a/d conversion is started after clearing module standby mode, wait for 10 ?clock cycles before starting. ? in active mode and sleep mode, the analog power supply current (ai stop1 ) flows in the ladder resistance even when the a/d converter is on standby. therefore, if the a/d converter is not used, it is recommended that av cc be connected to the system power supply and the adckstp (a/d converter module standby mode control) bit be cleared to 0 in clock stop register 1 (ckstpr1).
295 section 13 lcd controller/driver 13.1 overview the h8/3802 series has an on-chip segment type lcd control circuit, lcd driver, and power supply circuit, enabling it to directly drive an lcd panel. 13.1.1 features 1. features features of the lcd controller/driver are given below. ? display capacity duty cycle internal driver static 25 seg 1/2 25 seg 1/3 25 seg 1/4 25 seg ? lcd ram capacity 8 bits 13 bytes (104 bits) ? word access to lcd ram ? all four segment output pins can be used individually as port pins. ? common output pins not used because of the duty cycle can be used for common double- buffering (parallel connection). ? display possible in operating modes other than standby mode ? choice of 11 frame frequencies ? built-in power supply split-resistance, supplying lcd drive power ? use of module standby mode enables this module to be placed in standby mode independently when not used. ? a or b waveform selectable by software
296 13.1.2 block diagram figure 13.1 shows a block diagram of the lcd controller/driver. ?2 to ?256 w seg n lpcr lcr lcr2 display timing generator lcd ram (13 bytes) internal data bus 25-bit shift register lcd drive power supply segment driver common data latch common driver v 1 v 2 v 3 v ss com 1 com 4 seg 25 seg 1 notation: lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 v cc figure 13.1 block diagram of lcd controller/driver
297 13.1.3 pin configuration table 13.1 shows the lcd controller/driver pin configuration. table 13.1 pin configuration name abbrev. i/o function segment output pins seg 25 to seg 1 output lcd segment drive pins all pins are multiplexed as port pins (setting programmable) common output pins com 4 to com 1 output lcd common drive pins pins can be used in parallel with static or 1/2 duty lcd power supply pins v 1 , v 2 , v 3 used when a bypass capacitor is connected externally, and when an external power supply circuit is used 13.1.4 register configuration table 13.2 shows the register configuration of the lcd controller/driver. table 13.2 lcd controller/driver registers name abbrev. r/w initial value address lcd port control register lpcr r/w h'ffc0 lcd control register lcr r/w h'80 h'ffc1 lcd control register 2 lcr2 r/w h'ffc2 lcd ram r/w undefined h'f740 to h'f74c clock stop register 2 ckstpr2 r/w h'ff h'fffb
298 13.2 register descriptions 13.2.1 lcd port control register (lpcr) bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 4 w 3 sgs3 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w lpcr is an 8-bit read/write register which selects the duty cycle and lcd driver pin functions. bits 7 to 5: duty cycle select 1 and 0 (dts1, dts0), common function select (cmx) the combination of dts1 and dts0 selects static, 1/2, 1/3, or 1/4 duty. cmx specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. bit 7 dts1 bit 6 dts0 bit 5 cmx duty cycle common drivers notes 0 0 0 static com 1 (initial value) do not use com 4 , com 3 , and com 2 . 1 com 4 to com 1 com 4 , com 3 , and com 2 output the same waveform as com 1 . 0 1 0 1/2 duty com 2 to com 1 do not use com 4 and com 3 . 1 com 4 to com 1 com 4 outputs the same waveform as com 3 , and com 2 outputs the same waveform as com 1 . 1 0 0 1/3 duty com 3 to com 1 do not use com 4 . 1 com 4 to com 1 do not use com 4 . 1 1 0 1/4 duty com 4 to com 1 1 bit 4: reserved bit bit 4 is reserved; only 0 can be written to this bit. bits 3 to 0: segment driver select 3 to 0 (sgs3 to sgs0) bits 3 to 0 select the segment drivers to be used.
299 function of pins seg 25 to seg 1 bit 3 sgs3 bit 2 sgs2 bit 1 sgs1 bit 0 sgs0 seg 25 seg 24 to seg 21 seg 20 to seg 17 seg 16 to seg 13 seg 12 to seg 9 seg 8 to seg 5 seg 4 to seg 1 notes 0000 port port port port port port port (initial value) 1 port port port port port port seg 1 0 port port port port port seg seg 1 port port port port seg seg seg 1 0 0 port port port seg seg seg seg 1 port port seg seg seg seg seg 1 0 port seg seg seg seg seg seg 1 seg seg seg seg seg seg seg 1000segsegsegsegsegsegseg 1 seg seg seg seg seg seg port 1 0 seg seg seg seg seg port port 1 seg seg seg seg port port port 1 0 0 seg seg seg port port port port 1 seg seg port port port port port 10 seg port port port port port port 1 port port port port port port port
300 13.2.2 lcd control register (lcr) bit initial value read/write 7 1 6 psw 0 r/w 5 act 0 r/w 4 disp 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w lcr is an 8-bit read/write register which performs lcd drive power supply on/off control and display data control, and selects the frame frequency. lcr is initialized to h'80 upon reset. bit 7: reserved bit bit 7 is reserved; it is always read as 1 and cannot be modified. bit 6: lcd drive power supply on/off control (psw) bit 6 can be used to turn the lcd drive power supply off when lcd display is not required in a power-down mode, or when an external power supply is used. when the act bit is cleared to 0, or in standby mode, the lcd drive power supply is turned off regardless of the setting of this bit. bit 6 psw description 0 lcd drive power supply off (initial value) 1 lcd drive power supply on bit 5: display function activate (act) bit 5 specifies whether or not the lcd controller/driver is used. clearing this bit to 0 halts operation of the lcd controller/driver. the lcd drive power supply is also turned off, regardless of the setting of the psw bit. however, register contents are retained. bit 5 act description 0 lcd controller/driver operation halted (initial value) 1 lcd controller/driver operates
301 bit 4: display data control (disp) bit 4 specifies whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. bit 4 disp description 0 blank data is displayed (initial value) 1 lcd ram data is display bits 3 to 0: frame frequency select 3 to 0 (cks3 to cks0) bits 3 to 0 select the operating clock and the frame frequency. in subactive mode, watch mode, and subsleep mode, the system clock (? is halted, and therefore display operations are not performed if one of the clocks from ?2 to ?256 is selected. if lcd display is required in these modes, ?, ?/2, or ?/4 must be selected as the operating clock. bit 3 bit 2 bit 1 bit 0 frame frequency * 2 cks3 cks2 cks1 cks0 operating clock ?= 2 mhz ?= 250 khz * 1 0 * 00 w 128 hz * 3 (initial value) 0 * 01 w/2 64 hz * 3 0 * 1 * w/4 32 hz * 3 1000 /2 244 hz 1001 /4 977 hz 122 hz 1010 /8 488 hz 61 hz 1011 /16 244 hz 30.5 hz 1100 /32 122 hz 1101 /64 61 hz 1110 /128 30.5 hz 1111 /256 * : don t care notes: 1. this is the frame frequency in active (medium-speed, osc/16) mode when = 2 mhz. 2. when 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 3. this is the frame frequency when w = 32.768 khz.
302 13.2.3 lcd control register 2 (lcr2) bit initial value read/write 7 lcdab 0 r/w 6 1 5 1 4 w 3 w 0 w 2 w 1 w lcr2 is an 8-bit read/write register which controls switching between the a waveform and b waveform. bit 7: a waveform/b waveform switching control (lcdab) bit 7 specifies whether the a waveform or b waveform is used as the lcd drive waveform. bit 7 lcdab description 0 drive using a waveform (initial value) 1 drive using b waveform bits 6 and 5: reserved bits bits 6 and 5 are reserved; they are always read as 1 and cannot be modified. bits 4 to 0: reserved bits bits 4 to 0 are reserved; only 0 can be written to these bits.
303 13.2.4 clock stop register 2 (ckstpr2) b it i nitial value r ead/write 7 1 6 1 5 1 4 pw2ckstp 1 r/w 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 1 1 pw1ckstp 1 r/w ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the lcd controller/driver is described here. for details of the other bits, see the sections on the relevant modules. bit 0: lcd controller/driver module standby mode control (ldckstp) bit 0 controls setting and clearing of module standby mode for the lcd controller/driver. bit 0 ldckstp description 0 lcd controller/driver is set to module standby mode 1 lcd controller/driver module standby mode is cleared (initial value)
304 13.3 operation 13.3.1 settings up to lcd display to perform lcd display, the hardware and software related items described below must first be determined. 1. hardware settings a. using 1/2 duty when 1/2 duty is used, interconnect pins v 2 and v 3 as shown in figure 13.2. v cc v 1 v 2 v 3 v ss figure 13.2 handling of lcd drive power supply when using 1/2 duty b. large-panel display as the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. if the display lacks sharpness when using a large panel, refer to section 13.3.4, boosting the lcd drive power supply. when static or 1/2 duty is selected, the common output drive capability can be increased. set cmx to 1 when selecting the duty cycle. in this mode, with a static duty cycle pins com 4 to com 1 output the same waveform, and with 1/2 duty the com 1 waveform is output from pins com 2 and com 1 , and the com 2 waveform is output from pins com 4 and com 3 .
305 2. software settings a. duty selection any of four duty cycles?tatic, 1/2 duty, 1/3 duty, or 1/4 duty?an be selected with bits dts1 and dts0. b. segment selection the segment drivers to be used can be selected with bits sgs 3 to sgs 0 . c. frame frequency selection the frame frequency can be selected by setting bits cks 3 to cks 0 . the frame frequency should be selected in accordance with the lcd panel specification. for the clock selection method in watch mode, subactive mode, and subsleep mode, see 13.3.3, operation in power-down modes. d. a or b waveform selection either the a or b waveform can be selected as the lcd waveform to be used by means of lcdab.
306 13.3.2 relationship between lcd ram and display the relationship between the lcd ram and the display segments differs according to the duty cycle. lcd ram maps for the different duty cycles are shown in figures 13.3 to 13.6. after setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary ram, and display is started automatically when turned on. word- or byte-access instructions can be used for ram setting. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 2 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 seg 1 h'f740 h'f74c seg 25 seg 25 seg 25 seg 25 com 4 com 3 com 2 com 1 com 4 com 3 com 2 com 1 figure 13.3 lcd ram map (1/4 duty)
307 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 h'f740 h'f74c seg 25 seg 25 seg 25 com 3 com 2 com 1 com 3 com 2 com 1 space not used for display figure 13.4 lcd ram map (1/3 duty)
308 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 4 seg 4 seg 3 seg 3 seg 2 seg 2 seg 1 seg 1 h'f740 h'f746 h'f74c seg 25 seg 25 com 2 com 1 com 2 com 1 com 2 com 1 com 2 com 1 display space space not used for display figure 13.5 lcd ram map (1/2 duty) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 h'f740 h'f743 h'f74c seg 25 com 1 com 1 com 1 com 1 com 1 com 1 com 1 com 1 space not used for display display space figure 13.6 lcd ram map (static mode)
309 1 frame m data com 1 com 2 com 3 com 4 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty 1 frame m data com 1 com 2 com 3 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame m data com 1 com 2 seg n v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss 1 frame m data com 1 seg n v 1 v ss v 1 v ss (b) waveform with 1/3 duty (c) waveform with 1/2 duty (d) waveform with static output m: lcd alternation signal figure 13.7 output waveforms for each duty cycle (a waveform)
310 m data com 1 com 2 seg n v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss m data com 1 seg n v 1 v ss v 1 v ss (c) waveform with 1/2 duty m: lcd alternation signal (d) waveform with static output 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame (b) waveform with 1/3 duty m data com 3 seg n com 1 v 1 v 2 v 3 v ss com 2 v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty m data com 1 com 2 com 3 com 4 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame v 1 v 2, v 3 v ss figure 13.8 output waveforms for each duty cycle (b waveform)
311 table 13.3 output levels data 0 0 1 1 m0101 static common output v 1 v ss v 1 v ss segment output v 1 v ss v ss v 1 1/2 duty common output v 2 , v 3 v 2 , v 3 v 1 v ss segment output v 1 v ss v ss v 1 1/3 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 1/4 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 m: lcd alternation signal 13.3.3 operation in power-down modes in the h8/3802 series, the lcd controller/driver can be operated even in the power-down modes. the operating state of the lcd controller/driver in the power-down modes is summarized in table 13.4. in subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless ?, ?/2, or ?/4 has been selected by bits cks3 to cks0, the clock will not be supplied and display will halt. since there is a possibility that a direct current will be applied to the lcd panel in this case, it is essential to ensure that ?, ?/2, or ?/4 is selected. in active (medium-speed) mode, the system clock is switched, and therefore cks3 to cks0 must be modified to ensure that the frame frequency does not change.
312 table 13.4 power-down modes and display operation mode reset active sleep watch sub- active sub- sleep standby module standby clock runs runs runs stops stops stops stops stops * 4 w runs runs runs runs runs runs stops * 1 stops * 4 display act = 0 stops stops stops stops stops stops stops * 2 stops operation act = 1 stops functions functions functions * 3 functions * 3 functions * 3 stops * 2 stops notes: 1. the subclock oscillator does not stop, but clock supply is halted. 2. the lcd drive power supply is turned off regardless of the setting of the psw bit. 3. display operation is performed only if w, w/2, or w/4 is selected as the operating clock. 4. the clock supplied to the lcd stops. 13.3.4 boosting the lcd drive power supply when a large panel is driven, the on-chip power supply capacity may be insufficient. if the power supply capacity is insufficient when v cc is used as the power supply, the power supply impedance must be reduced. this can be done by connecting bypass capacitors of around 0.1 to 0.3 ? to pins v 1 to v 3 , as shown in figure 13.9, or by adding a split-resistance externally. h8/3802 series v cc v ss v 1 v 2 v 3 r r r r = several k ? to several m ? c= 0.1 to 0.3 f r figure 13.9 connection of external split-resistance
313 section 14 electrical characteristics 14.1 h8/3802 series absolute maximum ratings table 14.1 lists the absolute maximum ratings. table 14.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +7.0 v analog power supply voltage av cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.0 v input voltage ports other than port b, irqaec v in ?.3 to v cc +0.3 v port b av in ?.3 to av cc +0.3 v irqaec hv in ?.3 to +7.3 v operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability.
314 14.2 h8/3802 series electrical characteristics 14.2.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 3.0 5.5 v cc (v) f w (khz) all operating note 2: when an oscillator is used for the subclock, hold v cc at 2.2 v to 5.5 v from power-on until the oscillation settling time has elapsed. 32.768 4.5 16.0 2.0 10.0 4.0 1.8 2.7 4.5 5.5 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode note 1: the fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 mhz.
315 2. power supply voltage and operating frequency range subactive mode subsleep mode (except cpu) watch mode (except cpu) 16.384 8.192 4.096 1.8 3.6 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 8.0 (0.5) 5.0 2.0 1.0 1.8 2.7 4.5 5.5 v cc (v) (mhz) 1000 (7.8125) 625 250 15.625 1.8 2.7 4.5 5.5 v cc (v) (khz) note 1. the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 1 mhz. note 2. the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 15.625 khz. active (high-speed) mode sleep (high-speed) mode (except cpu) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter) 3. analog power supply voltage and a/d converter operating range (mhz) (0.5) 5.0 1.0 1.8 2.7 4.5 5.5 av cc (v) (khz) 500 1000 625 1.8 2.7 4.5 5.5 av cc (v) active (medium-speed) mode sleep (medium-speed) mode active (high-speed) mode sleep (high-speed) mode note 3: when av cc = 1.8 v to 2.7 v, the operating range is limited to = 1.0 mhz when using an oscillator, and is = 0.5 mhz to 1.0 mhz when using an external clock.
316 14.2.2 dc characteristics table 14.2 lists the dc characteristics of the h8/3802. table 14.2 dc characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input high v ih res v cc + 0.3 v v cc = 4.0 v to 5.5 v voltage wkp wkp irq irq v cc + 0.3 except the above rxd 32 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 except the above osc 1 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.9 v cc v cc + 0.3 except the above x 1 0.9 v cc v cc + 0.3 v v cc = 1.8 v to 5.5 v p3 1 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 , pa 0 to pa 3 0.7 v cc 0.8 v cc v cc + 0.3 v cc + 0.3 v v cc = 4.0 v to 5.5 v except the above pb 0 to pb 3 0.7 v cc av cc + 0.3 v cc = 4.0 v to 5.5 v 0.8 v cc av cc + 0.3 except the above irqaec 0.8 v cc 7.3 v v cc = 4.0 v to 5.5 v 0.9 v cc 7.3 except the above note: connect the test pin to v ss .
317 values item symbol applicable pins min typ max unit test condition notes input low v il res 0.3 0.2 v cc vv cc = 4.0 v to 5.5 v voltage wkp wkp irq irq 0.3 0.1 v cc except the above rxd 32 , 0.3 0.3 v cc vv cc = 4.0 v to 5.5 v 0.3 0.2 v cc except the above osc 1 0.3 0.2 v cc vv cc = 4.0 v to 5.5 v 0.3 0.1 v cc except the above x 1 0.3 0.1 v cc vv cc = 1.8 v to 5.5 v p3 1 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 , pa 0 to pa 3 , pb 0 to pb 3 0.3 0.3 0.3 v cc 0.2 v cc v v cc = 4.0 v to 5.5 v except the above output high voltage v oh p3 1 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 , pa 0 to pa 3 v cc 1.0 v cc 0.5 v cc 0.3 vv cc = 4.0 v to 5.5 v i oh = 1.0 ma v cc = 4.0 v to 5.5 v i oh = 0.5 ma i oh = 0.1 ma output low voltage v ol p4 0 to p4 2 0.6 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 , pa 0 to pa 3 0.5 i ol = 0.4 ma p3 1 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma
318 values item symbol applicable pins min typ max unit test condition notes output low voltage v ol p9 0 to p9 2 0.5 v v cc = 2.2 v to 5.5 v, i ol = 25 ma i ol = 15 ma i ol = 10 ma * 6 p9 3 to p9 5 0.5 i ol = 10 ma input/output | i il | res 20.0 ? v in = 0.5 v to * 2 leakage 1.0 v cc 0.5 v * 1 current osc 1 , x 1 , p3 1 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 , irqaec, p9 0 to p9 5 , pa 0 to pa 3 1.0 ? v in = 0.5 v to v cc 0.5 v pb 0 to pb 3 1.0 v in = 0.5 v to av cc 0.5 v pull-up mos i p p3 1 to p3 7 , p5 0 to p5 7 , 50.0 300.0 ? v cc = 5 v, v in = 0 v current p6 0 to p6 7 35.0 v cc = 2.7 v, v in = 0 v reference value input capacitance c in all input pins except power supply, res 15.0 pf f = 1 mhz, v in =0 v, t a = 25 c irqaec 30.0 res 80.0 * 2 15.0 * 1 p4 3 50.0 * 2 15.0 * 1 pb 0 to pb 3 15.0
319 values item symbol applicable pins min typ max unit test condition notes active mode current dissipation i ope1 v cc 7.0 10.0 ma active (high-speed) mode v cc = 5 v, f osc = 10 mhz * 3 * 4 i ope2 v cc 2.2 3.0 ma active (medium- speed) mode v cc = 5 v, f osc = 10 mhz osc /128 * 3 * 4 sleep mode current dissipation i sleep v cc 3.8 5.0 ma v cc =5 v, f osc = 10 mhz * 3 * 4 subactive mode current dissipation i sub v cc 15.0 30.0 ? v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4 8.0 ? v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) * 3 * 4 reference value subsleep mode current dissipation i subsp v cc 7.5 16.0 ? v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4 watch mode current dissipation i watch v cc 3.8 6.0 ? v cc = 2.7 v 3 2 khz crystal oscillator lcd not used * 2 * 3 * 4 2.8 * 1 * 3 * 4 standby mode current dissipation i stby v cc 1.0 5.0 ? 32 khz crystal oscillator not used * 3 * 4 ram data retaining voltage v ram v cc 1.5 v
320 values item symbol applicable pins min typ max unit test condition notes allowable output low current i ol output pins except port 3 and 9 2.0 ma v cc = 4.0 v to 5.5 v (per pin) port 3 10.0 v cc = 4.0 v to 5.5 v output pins except port 9 0.5 allowable output low i ol p9 0 to p9 2 25.0 ma v cc = 2.2 v to 5.5 v * 5 current (per pin) 15.0 10.0 p9 3 to p9 5 10.0 allowable output low current 40.0 ma v cc = 4.0 v to 5.5 v (total) port 3 80.0 v cc = 4.0 v to 5.5 v output pins except port 9 20.0 port 9 80.0 allowable i oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v output high current (per pin) 0.2 except the above allowable i oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v output high 10.0 except the above notes: 1. applies to the mask rom products. 2. applies to the hd6473802.
321 3. pin states during current measurement. mode res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc operates v cc halted system clock oscillator: crystal active (medium- speed) mode (i ope2 ) subclock oscillator: pin x 1 = gnd sleep mode v cc only timers operate v cc halted subactive mode v cc operates v cc halted system clock oscillator: subsleep mode v cc only timers operate, cpu stops v cc halted crystal subclock oscillator: watch mode v cc only time base operates, cpu stops v cc halted crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd 4. excludes current in pull-up mos transistors and output buffers. 5. when the pioff bit in the port mode register 9 is 0. 6. when the pioff bit in the port mode register 9 is 1.
322 14.2.3 ac characteristics table 14.3 lists the control signal timing, and tables 14.4 lists the serial interface timing of the h8/3802. table 14.3 control signal timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure system clock f osc osc 1 , osc 2 2.0 16.0 mhz v cc = 4.5 v to 5.5 v oscillation 2.0 10.0 v cc = 2.7 v to 5.5 v frequency 2.0 4.0 except the above osc clock ( osc ) cycle time t osc osc 1 , osc 2 62.5 500 (1000) ns v cc = 4.5 v to 5.5 v figure 14.1 100 500 (1000) v cc = 2.7 v to 5.5 v * 2 250 500 (1000) except the above system clock ( )t cyc 2 128 t osc cycle time 128 ? subclock oscillation frequency f w x 1 , x 2 32.768 or 38.4 khz watch clock ( w ) cycle time t w x 1 , x 2 30.5 or 26.0 ? figure 14.1 subclock ( sub ) cycle time t subcyc 2 8t w * 1 instruction cycle time 2 t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 20 45 ? figure 14.7 v cc = 2.2 v to 5.5 v figure 14.7 50 ms except the above figure 14.7
323 applicable values reference item symbol pins min typ max unit test condition figure oscillation stabilization time t rc x 1 , x 2 2.0 s v cc = 2.7 v to 5.5 v * 3 10.0 v cc = 2.7 v to 5.5 v external clock high t cph osc 1 25 ns v cc = 4.5 v to 5.5 v figure 14.1 width 40 v cc = 2.7 v to 5.5 v 100 except the above figure 14.1 x 1 15.26 or 13.02 ? external clock low t cpl osc 1 25 ns v cc = 4.5 v to 5.5 v figure 14.1 width 40 v cc = 2.7 v to 5.5 v 100 except the above figure 14.1 x 1 15.26 or 13.02 ? external clock rise t cpr osc 1 6nsv cc = 4.5 v to 5.5 v figure 14.1 time 10 v cc = 2.7 v to 5.5 v 25 except the above figure 14.1 x 1 55.0 ns external clock fall t cpf osc 1 6nsv cc = 4.5 v to 5.5 v figure 14.1 time 10 v cc = 2.7 v to 5.5 v 25 except the above figure 14.1 x 1 55.0 ns pin res res t cyc figure 14.2 input pin high width t ih irq irq wkp wkp t cyc t subcyc figure 14.3 aevl, aevh 0.5 t osc input pin low width t il irq irq wkp wkp t cyc t subcyc figure 14.3 aevl, aevh 0.5 t osc notes: 1. selected with sa1 and sa0 of system clock control register 2 (syscr2). 2. the figure in parentheses applies when an external clock is used. 3. after powering on, hold v cc at 2.2 v to 5.5 v until the chip's oscillation settling time has elapsed.
324 table 14.4 serial interface (sci3) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise indicated. values reference item symbol min typ max unit test conditions figure input clock asynchronous t scyc 4 t cyc or figure 14.4 cycle synchronous 6 t subcyc input clock pulse width t sckw 0.4 0.6 t scyc figure 14.4 transmit data delay time t txd 1t cyc or v cc = 4.0 v to 5.5 v figure 14.5 (synchronous) 1t subcyc except the above receive data setup time t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 (synchronous) 400.0 except the above figure 14.5 receive data hold time t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 (synchronous) 400.0 except the above figure 14.5
325 14.2.4 a/d converter characteristics table 14.5 shows the a/d converter characteristics of the h8/3802. table 14.5 a/d converter characteristics v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? unless otherwise indicated. applicable values reference item symbol pins min typ max unit test condition figure analog power supply voltage av cc av cc 1.8 5.5 v * 1 analog input voltage av in an 0 to an 3 0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5 v supply current ai stop1 av cc 600 ? * 2 reference value ai stop2 av cc 5a * 3 analog input capacitance c ain an 0 to an 3 15.0 pf allowable signal source impedance r ain 10.0 k ? 10 bit nonlinearity error ?.5 lsb av cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v ?.5 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v ?.5 except the above * 4 quantization error ?.5 lsb
326 applicable values reference item symbol pins min typ max unit test condition figure absolute accuracy ?.0 lsb av cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v ?.0 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v ?.0 except the above * 4 conversion time 12.4 124 ? av cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v 62 124 except the above notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. conversion time 62 ?
327 14.2.5 lcd characteristics table 14.6 shows the lcd characteristics. table 14.6 lcd characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75? (including subactive mode) unless otherwise specified. applicable test values reference item symbol pins conditions min typ max unit figure segment driver drop voltage v ds seg 1 to seg 25 i d = 2 a v 1 = 2.7 v to 5.5 v 0.6 v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 ? v 1 = 2.7 v to 5.5 v 0.3 v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 0.5 3.0 9.0 m ? 5.5 v * 2 notes: 1. the voltage drop from power supply pins v 1 , v 2 , v 3 , and vss to each segment pin or common pin. 2. when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v cc
328 14.3 operation timing figures 14.1 to 14.5 show timing diagrams. t , tw osc v ih v il t cph t cpl t cpr osc1 x 1 t cpf figure 14.1 clock input timing res figure 14.2 res low width v ih v il t il i rq irq w kp wkp figure 14.3 input timing
329 t scyc t sckw 32 sck figure 14.4 sck3 input clock timing 32 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * * v ol oh ol sck txd 32 (transmit data) rxd 32 (receive data) note: * output timing reference levels output high output low load conditions are shown in figure 14.6. v = 1/2vcc + 0.2 v v = 0.8 v figure 14.5 sci3 synchronous mode input/output timing
330 14.4 output load circuit v cc 2.4 k ? ? figure 14.6 output load condition 14.5 resonator equivalent circuit c s c o frequency (mhz) r s (max) c o (max) 4.193 100 ? ? figure 14.7 resonator equivalent circuit
331 14.6 usage note the ztat and mask rom versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, and so on. when system evaluation testing is carried out using the ztat version, the same evaluation testing should also be conducted for the mask rom version when changing over to that version.
332
333 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition subtraction multiplication division logical and logical or exclusive logical or move logical complement condition code notation symbol ? modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result
334 table a.1 lists the h8/300l cpu instruction set. table a.1 instruction set mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 rd8 2 0 2 mov.b rs, rd b rs8 rd8 2 0 2 mov.b @rs, rd b @rs16 rd8 2 0 4 mov.b @(d:16, rs), rd b @(d:16, rs16) rd8 4 0 6 mov.b @rs+, rd b @rs16 rd8 2 0 6 rs16+1 rs16 mov.b @aa:8, rd b @aa:8 rd8 2 0 4 mov.b @aa:16, rd b @aa:16 rd8 4 0 6 mov.b rs, @rd b rs8 @rd16 2 0 4 mov.b rs, @(d:16, rd) b rs8 @(d:16, rd16) 4 0 6 mov.b rs, @ rd b rd16 1 rd16 2 0 6 rs8 @rd16 mov.b rs, @aa:8 b rs8 @aa:8 2 0 4 mov.b rs, @aa:16 b rs8 @aa:16 4 0 6 mov.w #xx:16, rd w #xx:16 rd 4 0 4 mov.w rs, rd w rs16 rd16 2 0 2 mov.w @rs, rd w @rs16 rd16 2 0 4 mov.w @(d:16, rs), rd w @(d:16, rs16) rd16 4 0 6 mov.w @rs+, rd w @rs16 rd16 2 0 6 rs16+2 rs16 mov.w @aa:16, rd w @aa:16 rd16 4 0 6 mov.w rs, @rd w rs16 @rd16 2 0 4 mov.w rs, @(d:16, rd) w rs16 @(d:16, rd16) 4 0 6 mov.w rs, @ rd w rd16 2 rd16 2 0 6 rs16 @rd16 mov.w rs, @aa:16 w rs16 @aa:16 4 0 6 pop rd w @sp rd16 2 0 6 sp+2 sp push rs w sp 2 sp 2 0 6 rs16 @sp #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
335 mnemonic operation i h n z v c add.b #xx:8, rd b rd8+#xx:8 rd8 2 2 add.b rs, rd b rd8+rs8 rd8 2 2 add.w rs, rd w rd16+rs16 rd16 2 (1) 2 addx.b #xx:8, rd b rd8+#xx:8 +c rd8 2 (2) 2 addx.b rs, rd b rd8+rs8 +c rd8 2 (2) 2 adds.w #1, rd w rd16+1 rd16 2 2 adds.w #2, rd w rd16+2 rd16 2 2 inc.b rd b rd8+1 rd8 2 2 daa.b rd b rd8 decimal adjust rd8 2 ** (3) 2 sub.b rs, rd b rd8 rs8 rd8 2 2 sub.w rs, rd w rd16 rs16 rd16 2 (1) 2 subx.b #xx:8, rd b rd8 #xx:8 c rd8 2 (2) 2 subx.b rs, rd b rd8 rs8 c rd8 2 (2) 2 subs.w #1, rd w rd16 1 rd16 2 2 subs.w #2, rd w rd16 2 rd16 2 2 dec.b rd b rd8 1 rd8 2 2 das.b rd b rd8 decimal adjust rd8 2 ** 2 neg.b rd b 0 rd rd 2 2 cmp.b #xx:8, rd b rd8 #xx:8 2 2 cmp.b rs, rd b rd8 rs8 2 2 cmp.w rs, rd w rd16 rs16 2 (1) 2 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
336 mnemonic operation i h n z v c mulxu.b rs, rd b rd8 rs8 rd16 2 14 divxu.b rs, rd b rd16 rs8 rd16 2 (5) (6) 14 (rdh: remainder, rdl: quotient) and.b #xx:8, rd b rd8 #xx:8 rd8 2 0 2 and.b rs, rd b rd8 rs8 rd8 2 0 2 or.b #xx:8, rd b rd8 #xx:8 rd8 2 0 2 or.b rs, rd b rd8 rs8 rd8 2 0 2 xor.b #xx:8, rd b rd8 #xx:8 rd8 2 0 2 xor.b rs, rd b rd8 rs8 rd8 2 0 2 not.b rd b rd rd 2 0 2 shal.b rd b 2 2 shar.b rd b 2 02 shll.b rd b 2 02 shlr.b rd b 2 002 rotxl.b rd b 2 02 rotxr.b rd b 2 02 b 7 b 0 0 c c b 7 b 0 b 7 b 0 0 c b 7 b 0 0c c b 7 b 0 c b 7 b 0 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?????? ?
337 mnemonic operation i h n z v c rotl.b rd b 2 02 rotr.b rd b 2 02 bset #xx:3, rd b (#xx:3 of rd8) 12 2 bset #xx:3, @rd b (#xx:3 of @rd16) 14 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) 14 8 bset rn, rd b (rn8 of rd8) 12 2 bset rn, @rd b (rn8 of @rd16) 14 8 bset rn, @aa:8 b (rn8 of @aa:8) 14 8 bclr #xx:3, rd b (#xx:3 of rd8) 02 2 bclr #xx:3, @rd b (#xx:3 of @rd16) 04 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) 04 8 bclr rn, rd b (rn8 of rd8) 02 2 bclr rn, @rd b (rn8 of @rd16) 04 8 bclr rn, @aa:8 b (rn8 of @aa:8) 04 8 bnot #xx:3, rd b (#xx:3 of rd8) 2 2 ( #xx:3 of rd8 ) bnot #xx:3, @rd b (#xx:3 of @rd16) 4 8 ( #xx:3 of @rd16 ) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) 4 8 ( #xx:3 of @aa:8 ) bnot rn, rd b (rn8 of rd8) 2 2 ( rn8 of rd8 ) bnot rn, @rd b (rn8 of @rd16) 4 8 ( rn8 of @rd16 ) bnot rn, @aa:8 b (rn8 of @aa:8) 4 8 ( rn8 of @aa:8 ) #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size c b 7 b 0 c b 7 b 0 ? ? ? ? ? ?
338 mnemonic operation i h n z v c btst #xx:3, rd b ( #xx:3 of rd8 ) z2 2 btst #xx:3, @rd b ( #xx:3 of @rd16 ) z4 6 btst #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) z4 6 btst rn, rd b ( rn8 of rd8 ) z2 2 btst rn, @rd b ( rn8 of @rd16 ) z4 6 btst rn, @aa:8 b ( rn8 of @aa:8 ) z4 6 bld #xx:3, rd b (#xx:3 of rd8) c2 2 bld #xx:3, @rd b (#xx:3 of @rd16) c4 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) c4 6 bild #xx:3, rd b ( #xx:3 of rd8 ) c2 2 bild #xx:3, @rd b ( #xx:3 of @rd16 ) c4 6 bild #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) c4 6 bst #xx:3, rd b c (#xx:3 of rd8) 2 2 bst #xx:3, @rd b c (#xx:3 of @rd16) 4 8 bst #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 8 bist #xx:3, rd b c (#xx:3 of rd8) 2 2 bist #xx:3, @rd b c (#xx:3 of @rd16) 4 8 bist #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 8 band #xx:3, rd b c (#xx:3 of rd8) c2 2 band #xx:3, @rd b c (#xx:3 of @rd16) c4 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 6 biand #xx:3, rd b c ( #xx:3 of rd8 ) c2 2 biand #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 6 biand #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 6 bor #xx:3, rd b c (#xx:3 of rd8) c2 2 bor #xx:3, @rd b c (#xx:3 of @rd16) c4 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 6 bior #xx:3, rd b c ( #xx:3 of rd8 ) c2 2 bior #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 6 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
339 mnemonic operation i h n z v c bior #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 6 bxor #xx:3, rd b c (#xx:3 of rd8) c2 2 bxor #xx:3, @rd b c (#xx:3 of @rd16) c4 6 bxor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 6 bixor #xx:3, rd b c ( #xx:3 of rd8 ) c2 2 bixor #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 6 bixor #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 6 bra d:8 (bt d:8) pc pc+d:8 2 4 brn d:8 (bf d:8) pc pc+2 2 4 bhi d:8 c z = 0 2 4 bls d:8 c z = 1 2 4 bcc d:8 (bhs d:8) c = 0 2 4 bcs d:8 (blo d:8) c = 1 2 4 bne d:8 z = 0 2 4 beq d:8 z = 1 2 4 bvc d:8 v = 0 2 4 bvs d:8 v = 1 2 4 bpl d:8 n = 0 2 4 bmi d:8 n = 1 2 4 bge d:8 n v = 0 2 4 blt d:8 n v = 1 2 4 bgt d:8 z (n v) = 0 2 4 ble d:8 z (n v) = 1 2 4 jmp @rn pc rn16 2 4 jmp @aa:16 pc aa:16 4 6 jmp @@aa:8 pc @aa:8 2 8 bsr d:8 sp 2 sp 2 6 pc @sp pc pc+d:8 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size if condition is true then pc pc+d:8 else next; branching condition ? ? ? ? ? ? ?
340 mnemonic operation i h n z v c jsr @rn sp 2 sp 2 6 pc @sp pc rn16 jsr @aa:16 sp 2 sp 4 8 pc @sp pc aa:16 jsr @@aa:8 sp 2 sp 2 8 pc @sp pc @aa:8 rts pc @sp 2 8 sp+2 sp rte ccr @sp 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10 sp+2 sp pc @sp sp+2 sp sleep transit to sleep mode. 2 2 ldc #xx:8, ccr b #xx:8 ccr 2 2 ldc rs, ccr b rs8 ccr 2 2 stc ccr, rd b ccr rd8 2 2 andc #xx:8, ccr b ccr #xx:8 ccr 2 2 orc #xx:8, ccr b ccr #xx:8 ccr 2 2 xorc #xx:8, ccr b ccr #xx:8 ccr 2 2 nop pc pc+2 2 2 eepmov if r4l 04 (4) repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l 1 r4l until r4l=0 else next; notes: (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) the number of states required for execution is 4n + 9 (n = value of r4l). (5) set to 1 if the divisor is negative; otherwise cleared to 0. (6) set to 1 if the divisor is zero; otherwise cleared to 0. #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size
341 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
342 high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * note: bit-manipulation instructions the push and pop instructions are identical in machine language to mov instructions. * table a.2 operation code map
343 a.3 number of execution states the tables here can be used to calculate the number of states required for instruction execution. table a.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table a.3 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8
344 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 1 note: * depends on which on-chip module is accessed. see 2.9.1, notes on data access for details.
345 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1
346 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1
347 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16, rs), rd 2 1 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @ rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 note: * n: initial value in r4l. the source and destination operands are accessed n + 1 times each.
348 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @ rd 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 pop pop rd 1 1 2 push push rs 1 1 2 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1
349 appendix b internal i/o registers b.1 addresses lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'80 h'81 h'82 h'83 h'84 h'85 h'86 h'87 h'88 h'89 h'8a h'8b h'8c ecpwcrh ecpwcrh7 ecpwcrh6 ecpwcrh5 ecpwcrh4 ecpwcrh3 ecpwcrh2 ecpwcrh1 ecpwcrh0 asynchronous h'8d ecpwcrl ecpwcrl7 ecpwcrl6 ecpwcrl5 ecpwcrl4 ecpwcrl3 ecpwcrl2 ecpwcrl1 ecpwcrl0 event counter h'8e ecpwdrh ecpwdrh7 ecpwdrh6 ecpwdrh5 ecpwdrh4 ecpwdrh3 ecpwdrh2 ecpwdrh1 ecpwdrh0 h'8f ecpwdrl ecpwdrl7 ecpwdrl6 ecpwdrl5 ecpwdrl4 ecpwdrl3 ecpwdrl2 ecpwdrl1 ecpwdrl0 h'90 wegr wkegs7 wkegs6 wkegs5 wkegs4 wkegs3 wkegs2 wkegs1 wkegs0 system control h'91 spcr spc32 scinv3 scinv2 sci h'92 aegsr ahegs1 ahegs0 alegs1 alegs0 aiegs1 aiegs0 ecpwme asynchronous h'93 event counter h'94 eccr ackh1 ackh0 ackl1 ackl0 pwck2 pwck1 pwck0 h'95 eccsr ovh ovl ch2 cueh cuel crch crcl h'96 ech ech7 ech6 ech5 ech4 ech3 ech2 ech1 ech0 h'97 ecl ecl7 ecl6 ecl5 ecl4 ecl3 ecl2 ecl1 ecl0 h'98 h'99 h'9a h'9b h'9c h'9d h'9e h'9f h'a0 h'a1
350 lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'a2 h'a3 h'a4 h'a5 h'a6 h'a7 h'a8 smr com chr pe pm stop mp cks1 cks0 sci h'a9 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 h'aa scr3 tie rie te re mpie teie cke1 cke0 h'ab tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 h'ac ssr tdre rdrf oer fer per tend mpbr mpbt h''ad rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 h'ae h'af h'b0 tma tma3 tma2 tma1 tma0 timer a h'b1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 h'b2 h'b3 h'b4 h'b5 h'b6 tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f h'b7 tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl h'b8 tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 h'b9 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 h'ba ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 h'bb ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 h'bc h'bd h'be h'bf h'c0 lpcr dts1 dts0 cmx sgs3 sgs2 sgs1 sgs0 lcd controller/ h'c1 lcr psw act disp cks3 cks2 cks1 cks0 driver h'c2 lcr2 lcdab h'c3 h'c4 adrrh adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 a/d converter h'c5 adrrl adr1 adr0 h'c6 amr cks ch3 ch2 ch1 ch0 h'c7 adsr adsf h'c8 i/o port h'c9 pmr2 pof1 irq0
351 lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'ca pmr3 aevl aevh tmofh tmofl i/o port h'cb h'cc pmr5 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 h'cd pwcr2 pwcr21 pwcr20 10 bit pwm2 h'ce pwdru2 pwdru21 pwdru20 h'cf pwdrl2 pwdrl27 pwdrl26 pwdrl25 pwdrl24 pwdrl23 pwdrl22 pwdrl21 pwdrl20 h'd0 pwcr1 pwcr11 pwcr10 10 bit pwm1 h'd1 pwdru1 pwdru11 pwdru10 h'd2 pwdrl1 pwdrl17 pwdrl16 pwdrl15 pwdrl14 pwdrl13 pwdrl12 pwdrl11 pwdrl10 h'd3 i/o port h'd4 h'd5 h'd6 pdr3 p37 p36 p35 p34 p33 p32 p31 h'd7 pdr4 p43p42p41p40 h'd8 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 h'd9 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 h'da pdr7 p77 p76 p75 p74 p73 p72 p71 p70 h'db pdr8 ?80 h'dc pdr9 p95 p94 p93 p92 p91 p90 h'dd pdra pa3pa2pa1pa0 h'de pdrb pb3pb2pb1pb0 h'df h'e0 h'e1 pucr3 pucr37 pucr36 pucr35 pucr34 pucr33 pucr32 pucr31 h'e2 pucr5 pucr57 pucr56 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 h'e3 pucr6 pucr67 pucr66 pucr65 pucr64 pucr63 pucr62 pucr61 pucr60 h'e4 h'e5 h'e6 pcr3 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 h'e7 pcr4 pcr42 pcr41 pcr40 h'e8 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 h'e9 pcr6 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 h'ea pcr7 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 h'eb pcr8 pcr80 h'ec pmr9 pioff pwm2 pwm1 h'ed pcra pcra3 pcra2 pcra1 pcra0 h'ee pmrb irq1 h'ef h'f0 syscr1 ssby sts2 sts1 sts0 lson ma1 ma0 system control h'f1 syscr2 nesel dton mson sa1 sa0
352 lower register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'f2 iegr ieg1 ieg0 system control h'f3 ienr1 ienta ienwp ienec2 ien1 ien0 h'f4 ienr2 iendt ienad ientfh ientfl ienec h'f5 h'f6 irr1 irrta irrec2 irri1 irri0 h'f7 irr2 irrdt irrad irrtfh irrtfl irrec h'f8 h'f9 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 system control h'fa ckstpr1 s32ckstp adckstp tfckstp tackstp h'fb ckstpr2 pw2ckstp aeckstp pw1ckstp ldckstp h'fc h'fd h'fe h'ff legend sci: serial communication interface
353 b.2 functions bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 0 w tcrf timer control register f h'b6 timer f toggle output level l set to low level set to high level 16-bit mode, counts on tcfl overflow signal internal clock: /32 internal clock: /16 internal clock: /4 internal clock: w/4 0 1 toggle output level h 0 1 set to low level set to high level clock select h 0 1 1 1 1 * 0 0 1 1 * 0 1 0 1 counts on external event (tmif) rising/ falling edge clock select l 1 1 1 1 0 0 1 1 0 1 0 1 internal clock: /32 internal clock: /16 internal clock: /4 internal clock: w/4 0 ** * don t care r w r/w read only write only read and write see relevant register description possible types of access initial bit values dashes ( ) indicate undefined bits. bit numbers register acronym register name address to which the register is mapped name of on-chip supporting module names of the bits. dashes ( ) indicate reserved bits. full name of bit descriptions of bit settings
354 ecpwcrh?vent counter pwm compare register h h'8c aec bit initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 ecpwcrh7 ecpwcrh6 ecpwcrh5 ecpwcrh4 ecpwcrh3 ecpwcrh2 ecpwcrh1 ecpwcrh0 1 r/w sets event counter pwm waveform conversion period ecpwcrl?vent counter pwm compare register l h'8d aec ecpwcrl7 ecpwcrl6 ecpwcrl5 ecpwcrl4 ecpwcrl3 ecpwcrl2 ecpwcrl1 ecpwcrl0 11111111 bit initial value r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 r/w sets event counter pwm waveform conversion period ecpwdrh?vent counter pwm data register h h'8e aec ecpwdrh7 ecpwdrh6 ecpwdrh5 ecpwdrh4 ecpwdrh3 ecpwdrh2 ecpwdrh1 ecpwdrh0 bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w controls event counter pwm waveform generator data ecpwdrl?vent counter pwm data register l h'8f aec bit initial value r/w 76543210 ecpwdrl7 ecpwdrl6 ecpwdrl5 ecpwdrl4 ecpwdrl3 ecpwdrl2 ecpwdrl1 ecpwdrl0 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 w controls event counter pwm waveform generator data
355 wegr?akeup edge select register h'90 system control bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w 4 wkegs4 0 r/w wkpn edge selected 0 wkpn pin falling edge detected (n = 7 to 0) 1 wkpn pin rising edge detected 3 wkegs3 0 r/w
356 spcr?erial port control register h'91 sci bit initial value read/write 7 1 6 1 5 spc32 0 r/w 0 w 2 scinv2 0 r/w 1 w 4 w rxd 32 pin input data inversion switch 0 rxd 32 input data is not inverted 1 rxd 32 input data is inverted txd 32 pin output data inversion switch 0 txd 32 output data is not inverted 1 txd 32 output data is inverted p4 2 /txd 32 pin function switch 0 function as p4 2 i/o pin 1 function as txd 32 output pin 3 scinv3 0 r/w
357 aegsr?nput pin edge selection register h'92 aec bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 ahegs1 ahegs0 alegs1 alegs0 aiegs1 aiegs0 ecpwme 0 r/w reserved bit event counter pwm enable/disable, irqaec select/deselect 0 1 aec pwm halted, irqaec selected aec pwm operation enabled, irqaec deselected irqaec edge select bit 2 aiegs0 0 1 0 1 bit 3 aiegs1 0 0 1 1 falling edge on irqaec pin is sensed rising edge on irqaec pin is sensed both edges on irqaec pin are sensed use prohibited description aec edge select l bit 4 alegs0 0 1 0 1 bit 5 alegs1 0 0 1 1 falling edge on aevl pin is sensed rising edge on aevl pin is sensed both edges on aevl pin are sensed use prohibited description aec edge select h bit 6 ahegs0 0 1 0 1 bit 7 ahegs1 0 0 1 1 falling edge on aevh pin is sensed rising edge on aevh pin is sensed both edges on aevh pin are sensed use prohibited description
358 eccr?vent counter control register h'94 aec bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w r/w 1 0 0 ackh1 ackh0 ackl1 ackl0 pwck2 pwck1 pwck0 0 r/w reserved bit event counter pwm clock select bit 2 pwck1 0 0 1 1 * * bit 3 pwck2 0 0 0 0 0 0 /2 /4 /8 /16 /32 /64 description bit 1 pwck0 0 1 0 1 0 1 aec clock select l bit 4 ackl0 0 1 0 1 bit 5 ackl1 0 0 1 1 aevl pin input /2 /4 /8 description aec clock select h bit 6 ackh0 0 1 0 1 bit 7 ackh1 0 0 1 1 aevh pin input /2 /4 /8 description
359 eccsr?vent counter control/status register h'95 aec bit initial value read/write 7 ovh 0 r/w 6 ovl 0 r/w 5 0 r/w 0 crcl 0 r/w 2 cuel 0 r/w 1 crch 0 r/w 4 ch2 0 r/w counter reset control l 0 1 ecl is reset ecl reset is cleared and count-up function is enabled counter reset control h 0 ech is reset 1 ech reset is cleared and count-up function is enabled count-up enable l 0 ecl event clock input is disabled. ecl value is held 1 ecl event clock input is enabled count-up enable h 0 ech event clock input is disabled. ech value is held 1 ech event clock input is enabled channel select 0 ech and ecl are used together as a single- channel 16-bit event counter 1 ech and ecl are used as two independent 8-bit event counter channels counter overflow l 0 ecl has not overflowed 1 ecl has overflowed counter overflow h 0 ech has not overflowed 1 ech has overflowed 3 cueh 0 r/w
360 ech?vent counter h h'96 aec bit initial value read/write 7 ech7 0 r 6 ech6 0 r 5 ech5 0 r 0 ech0 0 r 2 ech2 0 r 1 ech1 0 r 4 ech4 0 r 3 ech3 0 r ecl?vent counter l h'97 aec bit initial value read/write 7 ecl7 0 r 6 ecl6 0 r 5 ecl5 0 r 0 ecl0 0 r 2 ecl2 0 r 1 ecl1 0 r 4 ecl4 0 r 3 ecl3 0 r
361 smr?erial mode register h'a8 sci3 bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 4 pm 0 r/w clock select 0 0 01 1 1 1 clock w/2 clock 0 /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data communication mode 0 asynchronous mode 1 synchronous mode 3 stop 0 r/w
362 brr?it rate register h'a9 sci3 bit initial value read/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w
363 scr3?erial control register3 h'aa sci3 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 4 re 0 r/w receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (normal receive operation) [clearing conditions] when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled the receive interrupt request (rxi), receive error interrupt request (eri), and setting of the rdrf, fer, and oer flags in the serial status register (ssr), are disabled until data with the multiprocessor bit set to 1 is received. transmit enable 0 transmit operation disabled (txd pin is transmit data pin) 1 transmit operation enabled (txd pin is transmit data pin) receive enable 0 receive operation disabled (rxd pin is i/o port) 1 receive operation enabled (rxd pin is receive data pin) transmit end interrupt enable clock enable 0 bit 1 cke1 0 0 1 1 bit 0 cke0 0 1 0 1 communication mode asynchronous synchronous asynchronous synchronous asynchronous synchronous asynchronous synchronous internal clock internal clock internal clock reserved (do not specify this combination) external clock external clock reserved (do not specify this combination) reserved (do not specify this combination) i/o port serial clock output clock output clock input serial clock input clock source sck pin function description transmit end interrupt request (tei) disabled 1 transmit end interrupt request (tei) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 3 mpie 0 r/w
364 tdr?ransmit data register h'ab sci3 bit initial value read/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w data for transfer to tsr
365 ssr?erial status register h'ac sci3 bit initial value read/write note: * only a write of 0 for flag clearing is possible. 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 oer 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r 4 fer 0 r/(w) * receive data register full 0 there is no receive data in rdr [clearing conditions] after reading rdrf = 1, cleared by writing 0 to rdrf when rdr data is read by an instruction 1 there is receive data in rdr [setting conditions] when reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 transmit data written in tdr has not been transferred to tsr [clearing conditions] after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmit data has not been written to tdr, or transmit data written in tdr has been transferred to tsr [setting conditions] when bit te in serial control register3 (scr3) is cleared to 0 when data is transferred from tdr to tsr transmit end 0 transmission in progress [clearing conditions] 1 transmission ended [setting conditions] parity error 0 reception in progress or completed normally [clearing conditions] after reading per = 1, cleared by writing 0 to per 1 a parity error has occurred during reception [setting conditions] framing error 0 reception in progress or completed normally [clearing conditions] after reading fer = 1, cleared by writing 0 to fer 1 a framing error has occurred during reception [setting conditions] when the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 overrun error 0 reception in progress or completed [clearing conditions] after reading oer = 1, cleared by writing 0 to oer 1 an overrun error has occurred during reception [setting conditions] when the next serial reception is completed with rdrf set to 1 multiprocessor bit receive multiprocessor bit transfer 0 data in which the multiprocessor bit is 0 has been received 1 data in which the multiprocessor bit is 1 has been received 0 a 0 multiprocessor bit is transmitted 1 a 1 multiprocessor bit is transmitted 3 per 0 r/(w) * after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction when bit te in serial control register3 (scr3) is cleared to 0 when bit tdre is set to 1 when the last bit of a transmit character is sent when the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (pm) in the serial mode register (smr)
366 rdr?eceive data register h'ad sci3 bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r tma?imer mode register a h'b0 timer a bit initial value read/write 7 w 6 w 5 w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 1 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 10 1 0 0 1 1 1 psw psw psw psw 00 1 0 0 1 1 psw and tca are reset 10 1 0 0 1 1 prescaler and divider ratio or overflow period /8192 /4096 /2048 /512 /256 /128 /32 /8 1 s 0.5 s 0.25 s 0.03125 s interval timer time base (when using 32.768 khz) function 3 tma3 0 r/w
367 tca?imer counter a h'b1 timer a bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value
368 tcrf?imer control register f h'b6 timer f bit initial value read/write 7 tolh 0 w 6 cksh2 0 w 5 cksh1 0 w 0 cksl0 0 w 2 cksl2 0 w 1 cksl1 0 w 4 cksh0 0 w clock select l internal clock /32 internal clock /16 internal clock /4 internal clock w/4 non-operationl use prohibited use prohibited use prohibited toggle output level l 0 low level 1 high level toggle output level h 0 low level 1 high level 3 toll 0 w clock select h 0 use prohibited internal clock /32 internal clock /16 internal clock /4 internal clock w/4 16-bit mode, counting on tcfl overflow signal 1 1 1 1 0 0 0 1 1 0 001 010 011 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
369 tcsrf?imer control/status register f h'b7 timer f bit initial value read/write note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. 7 ovfh 0 r/(w) 6 cmfh 0 r/(w) 5 ovieh 0 r/w 0 cclrl 0 r/w 2 cmfl 0 r/w 1 oviel 0 r/w 4 cclrh 0 r/w compare match flag h 0 clearing conditions: after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting conditions: set when the tcfh value matches the ocrfh value timer overflow flag h 0 clearing conditions: after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting conditions: set when tcfh overflows from h'ff to h'00 compare match flag l 0 clearing conditions: after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting conditions: set when the tcfl value matches the ocrfl value timer overflow flag l 0 clearing conditions: after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting conditions: set when tcfl overflows from h'ff to h'00 counter clear h 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled timer overflow interrupt enable h 0 tcfh overflow interrupt request is disabled 1 tcfh overflow interrupt request is enabled timer overflow interrupt enable l counter clear l 0 tcfl overflow interrupt request is disabled 1 tcfl overflow interrupt request is enabled 0 tcfl clearing by compare match is disabled 1 tcfl clearing by compare match is enabled 3 ovfl 0 r/(w) ** **
370 tcfh?-bit timer counter fh h'b8 timer f bit initial value read/write 7 tcfh7 0 r/w 6 tcfh6 0 r/w 5 tcfh5 0 r/w 4 tcfh4 0 r/w 3 tcfh3 0 r/w 0 tcfh0 0 r/w 2 tcfh2 0 r/w 1 tcfh1 0 r/w count value tcfl?-bit timer counter fl h'b9 timer f bit initial value read/write 7 tcfl7 0 r/w 6 tcfl6 0 r/w 5 tcfl5 0 r/w 4 tcfl4 0 r/w 3 tcfl3 0 r/w 0 tcfl0 0 r/w 2 tcfl2 0 r/w 1 tcfl1 0 r/w count value ocrfh?utput compare register fh h'ba timer f bit initial value read/write 7 ocrfh7 1 r/w 6 ocrfh6 1 r/w 5 ocrfh5 1 r/w 4 ocrfh4 1 r/w 3 ocrfh3 1 r/w 0 ocrfh0 1 r/w 2 ocrfh2 1 r/w 1 ocrfh1 1 r/w ocrfl?utput compare register fl h'bb timer f bit initial value read/write 7 ocrfl7 1 r/w 6 ocrfl6 1 r/w 5 ocrfl5 1 r/w 4 ocrfl4 1 r/w 3 ocrfl3 1 r/w 0 ocrfl0 1 r/w 2 ocrfl2 1 r/w 1 ocrfl1 1 r/w
371 lpcr?cd port control register h'c0 lcd controller/driver bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w 4 w clock enable 3 sgs3 0 r/w duty select, common function select bit 7 dts1 0 0 1 1 bit 6 dts0 0 1 0 1 bit 5 cmx 0 1 0 1 0 1 0 1 duty cycle static 1/2 duty 1/3 duty 1/4 duty common drivers com 1 com 4 to com 1 com 2 to com 1 com 4 to com 1 com 3 to com 1 com 4 to com 1 com 4 to com 1 com 4 to com 2 output the same waveform as com 1 com 4 outputs the same waveform as com 3 and com 2 outputs the same waveform as com 1 com 4 outputs a non-selected waveform notes port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 sgs3 bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 sgs2 bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 sgs1 bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sgs0 seg 25 seg 24 to seg 21 seg 20 to seg 17 seg 16 to seg 13 seg 12 to seg 9 seg 8 to seg 5 seg 4 to seg 1 function of pins seg 25 to seg 1 notes (initial value)
372 lcr?cd control register h'c1 lcd controller/driver bit initial value read/write 7 1 6 psw 0 r/w 5 act 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 4 disp 0 r/w lcd drive power supply on/off control frame frequency select operating clock bit 1 bit 2 bit 3 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 * 0 1 0 1 0 1 0 1 bit 1 cks1 cks2 cks3 cks0 w w/2 w/4 /2 /4 /8 /16 /32 /64 /128 /256 display function activate lcd controller/driver operation halted lcd controller/driver operates : don t care * 0 1 0 lcd drive power supply off 1 lcd drive power supply on display data control 0 blank data is displayed 1 lcd ram data is displayed
373 lcr2?cd control register 2 h'c2 lcd controller/driver bit initial value read/write 7 lcdab 0 r/w 6 1 5 1 3 w 0 w 2 w 1 w 4 w a waveform/b waveform switching control 0 drive using a waveform 1 drive using b waveform
374 amr?/d mode register h'c6 a/d converter bit initial value read/write 7 cks 0 r/w 6 0 r/w 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel * : don t care ch3 ch2 0 ch1 ch0 bit 1 bit 0 0 1 1 0 1 1 00 5 1 ** 100 1 10 1 an 0 an 1 an 2 an 3 clock select 62/ bit 7 0 conversion period cks 31/ 1 62 s = 1 mhz 31 s 12.4 s = 5 mhz * conversion time use prohibited *: operation is not guaranteed with a conversion time of less than 12.4 s. select a setting that gives a conversion time of at least 12.4 s.
375 adrrh?/d result register h h'c4 a/d converter adrrl?/d result register l h'c5 bit initial value read/write adrrh 7 adr9 not fixed r 6 adr8 not fixed r 5 adr7 not fixed r 3 adr5 not fixed r 0 adr2 not fixed r 2 adr4 not fixed r 1 adr3 not fixed r 4 adr6 not fixed r a/d conversion result bit initial value read/write adrrl 7 adr1 not fixed r 6 adr0 not fixed r 5 3 0 2 1 4 a/d conversion result adsr?/d start register h'c7 a/d converter bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 a/d status flag 0 1 read write read write indicates completion of a/d conversion stops a/d conversion indicates a/d conversion in progress starts a/d conversion
376 pmr2?ort mode register 2 h'c9 i/o port bit initial value read/write 7 1 6 1 5 0 r/w 4 1 3 1 2 1 0 pof1 irq0 0 r/w ww p4 3 / irq0 pin function switch functions as p4 3 i/o pin functions as irq 0 input pin 0 1 p3 5 pin output buffer pmos on/off control cmos output nmos open-drain output 0 1
377 pmr3?ort mode register 3 h'ca i/o port bit initial value read/write 7 aevl 0 r/w 6 aevh 0 r/w 5 w 3 w 0 w 2 tmofh 0 r/w 1 tmofl 0 r/w 4 w p3 2 /tmofh pin function switch 0 functions as p3 2 i/o pin 1 functions as tmofh output pin p3 1 /tmofl pin function switch 0 functions as p3 1 i/o pin 1 functions as tmofl output pin p3 6 /aevh pin function switch 0 functions as p3 6 i/o pin functions as aevh input pin 1 p3 7 /aevl pin function switch 0 functions as p3 7 i/o pin 1 functions as aevl input pin
378 pmr5?ort mode register 5 h'cc i/o port bit initial value read/write 7 wkp 7 0 r/w 6 wkp 6 0 r/w 5 wkp 5 0 r/w 3 wkp 3 0 r/w 0 wkp 0 0 r/w 2 wkp 2 0 r/w 1 wkp 1 0 r/w 4 wkp 4 0 r/w 0 functions as p5 n i/o pin p5 n / wkp n /seg n+1 pin function switch 1 functions as wkp n input pin pwcr2?wm2 control register h'cd 10-bit pwm cloxk select the input clock is (t * = 1/ ) the conversion period is 512/ , with a minimum modulation width of 1/2 the input clock is /2 (t * = 2/ ) the conversion period is 1,024/ , with a minimum modulation width of 1/ 0 1 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 2 1 1 0 w 0 pwcr21 pwcr20 0 w note: * t : period of pwm2 input clock the input clock is /4 (t * = 4/ ) the conversion period is 2,048/ , with a minimum modulation width of 2/ the input clock is /8 (t * = 8/ ) the conversion period is 4,096/ , with a minimum modulation width of 4/ 0 1 0 1 pwdru2?wm2 data register u h'ce 10-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 2 1 1 0 w 0 pwdru21 pwdru20 0 w upper 2 bits of pwm2 waveform generation data
379 pwdrl2?wm2 data register l h'cf 10-bit pwm bit initial value read/write 7 0 w 6 0 w pwdrl27 pwdrl26 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 pwdrl25 pwdrl24 pwdrl23 pwdrl22 pwdrl21 pwdrl20 0 w lower 8 bits of pwm2 waveform generation data pwcr1?wm1 control register h'd0 10-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr1 0 0 w 2 1 1 pwcr1 1 0 w clock select 0 the input clock is (t * = 1/ ) the conversion period is 512/ , with a minimum modulation width of 1/2 the input clock is /2 (t * = 2/ ) the conversion period is 1,024/ , with a minimum modulation width of 1/ 1 the input clock is /4 (t * = 4/ ) the conversion period is 2,048/ , with a minimum modulation width of 2/ the input clock is /8 (t * = 8/ ) the conversion period is 4,096/ , with a minimum modulation width of 4/ note: t : period of pwm input clock *
380 pwdru1?wm1 data register u h'd1 10-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 0 w 2 1 1 0 w upper 2 bits of data for generating pwm1 waveform pwdru1 0 pwdur1 1 pwdrl1?wm1 data register l h'd2 10-bit pwm bit initial value read/write 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w lower 8 bits of data for generating pwm1 waveform pwdrl1 5 pwdrl1 4 pwdrl1 3 pwdrl1 0 pwdrl1 2 pwdrl1 1 pwdrl1 6 pwdrl1 7 pdr3?ort data register 3 h'd6 i/o ports bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 2 p3 0 r/w 1 p3 0 r/w 2 3 4 5 6 7 1 stores data of port 3 pins pdr4?ort data register 4 h'd7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 30 21 reads p4 3 pin state stores data of port 4 pins
381 pdr5?ort data register 5 h'd8 i/o ports bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 30 21 4 5 6 7 stores data of port 5 pins pdr6?ort data register 6 h'd9 i/o ports bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 30 21 4 5 6 7 stores data of port 6 pins pdr7?ort data register 7 h'da i/o ports bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 3210 4 5 6 7 stores data of port 7 pins pdr8?ort data register 8 h'db i/o ports bit initial value read/write 7 6 5 4 3 0 p8 0 r/w 2 1 0 stores data of p8 0 pin
382 pdr9?ort data register 9 h'dc i/o ports bit initial value read/write 7 1 6 1 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 1 r/w stores data of port 9 pins pdra?ort data register a h'dd i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 30 21 stores data of port a pins pdrb?ort data register b h'de i/o ports bit initial value read/write 7 6 5 4 3 pb r 0 pb r 2 pb r 1 pb r 30 21 reads states of port b pins pucr3?ort pull-up control register 3 h'e1 i/o ports bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 w 2 pucr3 0 r/w 1 pucr3 0 r/w 2 3 4 5 6 7 1
383 pucr5?ort pull-up control register 5 h'e2 i/o ports bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 30 21 4 5 6 7 pucr6?ort pull-up control register 6 h'e3 i/o ports bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 30 21 4 5 6 7 pcr3?ort control register 3 h'e6 i/o ports bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 w 2 pcr3 0 w 1 pcr3 0 w port 3 input/output select 0 input pin 1 output pin 2 3 4 5 6 7 1 pcr4?ort control register 4 h'e7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w port 4 input/output select 0 input pin 1 output pin 0 21
384 pcr5?ort control register 5 h'e8 i/o ports bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 76543 0 21 pcr6?ort control register 6 h'e9 i/o ports bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 76543 0 21 pcr7?ort control register 7 h'ea i/o ports bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 7 65 432 10
385 pcr8?ort control register 8 h'eb i/o ports bit initial value read/write 7 w 6 w 5 w 4 w 3 w 0 pcr8 0 w 2 w 1 w port 8 input/output select 0 input pin 1 output pin 0 pmr9?ort mode register 9 h'ec i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 0 2 1 0 0 pioff pwm2 pwm1 0 r/w r/w w r/w p90/pwm1 pin function switch functions as p90 output pin functions as pwm1 output pin 0 1 p91/pwm2 pin function switch functions as p91 output pin functions as pwm2 output pin 0 1 p92 to p90 step-up circuit control large-current port step-up circuit is turned on large-current port step-up circuit is turned off 0 1
386 pcra?ort control register a h'ed i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pcra 0 w 0 pcra 0 w 2 pcra 0 w 1 pcra 0 w 0 1 2 3 port a input/output select 0 input pin 1 output pin pmrb?ort mode register b h'ee i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 irq1 0 r/w 0 1 2 1 1 1 pb 3 /an 3 /irq 1 pin function switch 0 functions as pb 3 /an 3 input pin 1 functions as irq 1 input pin
387 syscr1?ystem control register 1 h'f0 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 1 1 ma1 1 r/w 4 sts0 0 r/w software standby 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 1,024 states wait time = 2,048 states 10 1 active (medium-speed) mode clock select /16 /32 0 1 0 0 1 1 /64 /128 1 1 00 10 1 wait time = 4,096 states wait time = 2 states wait time = 8 states wait time = 16 states low speed on flag 0 the cpu operates on the system clock ( ) 1 the cpu operates on the subclock ( ) sub when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode when a sleep instruction is executed in subactive mode, a transition is made to watch mode osc osc osc osc
388 syscr2?ystem control register 2 h'f1 system control bit initial value read/write 7 1 6 1 5 1 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 1 r/w subactive mode clock select 0 /8 /4 0 1 1 /2 * w w w direct transfer on flag 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode 1 when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 medium speed on flag 0 operates in active (high-speed) mode 1 operates in active (medium-speed) mode noise elimination sampling frequency select 0 sampling rate is /16 1 sampling rate is /4 osc osc * : don t care
389 iegr?rq edge select register h'f2 system control bit initial value read/write 7 1 6 1 4 w 3 w 0 ieg0 0 r/w 2 w 1 ieg1 0 r/w 5 1 irq 0 edge select 0 falling edge of irq 0 pin input is detected rising edge of irq 0 pin input is detected 1 irq 1 edge select 0 falling edge of irq 1 pin input is detected rising edge of irq 1 pin input is detected 1
390 ienr1?nterrupt enable register 1 h'f3 system control bit initial value read/write 7 ienta 0 r/w 6 w 4 w 3 w 0 ien0 0 r/w 2 ienec2 0 r/w 1 ien1 0 r/w 5 ienwp 0 r/w irqaec interrupt enable 0 disables irqaec interrupt requests enables irqaec interrupt requests 1 wakeup interrupt enable 0 disables wkp 7 to wkp 0 interrupt requests enables wkp 7 to wkp 0 interrupt requests 1 timer a interrupt enable 0 disables timer a interrupt requests enables timer a interrupt requests 1 irq 1 to irq 0 interrupt enable 0 disables irq 1 to irq 0 interrupt, requests enables irq 1 to irq 0 interrupt requests 1
391 ienr2?nterrupt enable register 2 h'f4 system control bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 w 4 w asynchronous event counter interrupt enable 0 disables asynchronous event counter interrupt requests 1 enables asynchronous event counter interrupt requests timer fl interrupt enable 0 disables timer fl interrupt requests 1 enables timer fl interrupt requests timer fh interrupt enable 0 disables timer fh interrupt requests 1 enables timer fh interrupt requests a/d converter interrupt enable 0 disables a/d converter interrupt requests 1 enables a/d converter interrupt requests direct transition interrupt enable 0 disables direct transition interrupt requests 1 enables direct transition interrupt requests
392 irr1?nterrupt request register 1 h'f6 system control bit initial value read/write 7 irrta 0 r/w * 6 w 5 1 3 w 0 irri0 0 r/w * 2 irrec2 0 r/w * 1 irri1 0 r/w * 4 w irq1 to irq0 interrupt request flags 0 clearing conditions: when irrin = 1, it is cleared by writing 0 (n = 1 or 0) note: * bits 7 and 2 to 0 can only be written with 0, for flag clearing. 1 setting conditions: when pin irqn is designated for interrupt input and the designated signal edge is input timer a interrupt request flag 0 clearing conditions: when irrta = 1, it is cleared by writing 0 1 setting conditions: when the timer a counter value overflows (from h'ff to h'00) irqaec interrupt request flag 0 clearing conditions: when irrec2 = 1, it is cleared by writing 0 1 setting conditions: when pin irqaec is designated for interrupt input and the designated signal edge is input
393 irr2?nterrupt request register 2 h'f7 system control bit initial value read/write 7 irrdt 0 r/(w) * 6 irrad 0 r/(w) * 5 w 3 irrtfh 0 r/(w) * 0 irrec 0 r/(w) * 2 irrtfl 0 r/(w) * 1 w 4 w note: * bits 7, 6, 3, 2, and 0 can only be written with 0, for flag clearing. a/d converter interrupt request flag 0 clearing conditions: when irrad = 1, it is cleared by writing 0 1 setting conditions: when the a/d converter completes conversion and adsf is reset direct transition interrupt request flag 0 clearing conditions: when irrdt = 1, it is cleared by writing 0 1 setting conditions: when a sleep instruction is executed while dton is set to 1, and a direct transition is made timer fh interrupt request flag 0 clearing conditions: when irrtfh = 1, it is cleared by writing 0 1 setting conditions: when counter fh and output compare register fh match in 8-bit timer mode, or when 16-bit counters fl and fh and output compare registers fl and fh match in 16-bit timer mode timer fl interrupt request flag 0 clearing conditions: when irrtfl = 1, it is cleared by writing 0 1 setting conditions: when counter fl and output compare register fl match in 8-bit timer mode asynchronous event counter interrupt request flag 0 clearing conditions: when irrec = 1, it is cleared by writing 0 1 setting conditions: when the asynchronous event counter value overflows
394 iwpr?akeup interrupt request register h'f9 system control bit initial value read/write 7 iwpf7 0 r/(w) * 6 iwpf6 0 r/(w) * 5 iwpf5 0 r/(w) * 3 iwpf3 0 r/(w) * 0 iwpf0 0 r/(w) * 2 iwpf2 0 r/(w) * 1 iwpf1 0 r/(w) * 4 iwpf4 0 r/(w) * 0 clearing conditions: when iwpfn = 1, it is cleared by writing 0 (n = 7 to 0) note: * all bits can only be written with 0, for flag clearing. wakeup interrupt request register 1 setting conditions: when pin wkpn is designated for wakeup input and a falling edge is input at that pin
395 ckstpr1?lock stop register 1 h'fa system control bit initial value read/write 7 1 6 1 5 s32ckstp 1 r/w 3 1 0 tackstp 1 r/w 2 tfckstp 1 r/w 1 1 4 adckstp 1 r/w timer a module standby mode control timer f module standby mode control 0 timer f is set to module standby mode timer f module standby mode is cleared 1 a/d converter module standby mode control 0 a/d converter is set to module standby mode a/d converter module standby mode is cleared 1 0 timer a is set to module standby mode timer a module standby mode is cleared 1 sci3 module standby mode control 0 sci3 is set to module standby mode sci3 module standby mode is cleared 1
396 ckstpr2?lock stop register 2 h'fb system control bit initial value read/write 7 1 6 1 5 1 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 1 1 pw1ckstp 1 r/w 4 pw2ckstp 1 r/w lcd module standby mode control pwm2 module standby mode control 0 pwm2 is set to module standby mode pwm2 module standby mode is cleared 1 asynchronous event counter module standby mode control 0 asynchronous event counter is set to module standby mode asynchronous event counter module standby mode is cleared 1 pwm1 module standby mode control 0 pwm1 is set to module standby mode pwm1 module standby mode is cleared 1 0 lcd is set to module standby mode lcd module standby mode is cleared 1
397 appendix c i/o port block diagrams c.1 block diagrams of port 3 p3 n v cc v cc pucr3 n pmr3 n pdr3 n pcr3 n aec module internal data bus sby v ss aevh(p3 6 ) aevl(p3 7 ) pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 n=7 or 6 figure c.1 (a) port 3 block diagram (pins p3 7 and p3 6 )
398 p3 5 v cc v cc pucr3 5 pmr2 5 pdr3 5 pcr3 5 sby v ss internal data bus pdr3: pcr3: pucr3: pmr2 port data register 3 port control register 3 port pull-up control register 3 port mode register 2 figure c.1 (b) port 3 block diagram (pin p3 5 )
399 p3 n pdr3 n pucr3 pcr3 n sby v ss pdr3: port data register 3 pcr3: port control register 3 n = 4 or 3 internal data bus v cc v cc figure c.1 (c) port 3 block diagram (pins p3 4 and p3 3 )
400 p3 n v cc v cc pucr3 n internal data bus pmr3 n pdr3 n pcr3 n sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 n = 2 or 1 tmofh (p3 2 ) tmofl (p3 1 ) figure c.1 (d) port 3 block diagram (pins p3 2 and p3 1 )
401 c.2 block diagrams of port 4 p4 3 pmr3 3 internal data bus irq 0 pmr3: port mode register 3 figure c.2 (a) port 4 block diagram (pin p4 3 )
402 p4 2 sci3 module internal data bus pdr4 2 scinv3 pcr4 2 sby v ss pdr4: port data register 4 pcr4: port control register 4 txd32 v cc spc32 figure c.2 (b) port 4 block diagram (pin p4 2 )
403 p4 1 v cc sci3 module pdr4 1 pcr4 1 sby v ss pdr4: port data register 4 pcr4: port control register 4 re32 rxd32 internal data bus scinv2 figure c.2 (c) port 4 block diagram (pin p4 1 )
404 p4 0 v cc sci3 module pdr4 0 pcr4 0 sby v ss pdr4: port data register 4 pcr4: port control register 4 sckie32 sckoe32 scko32 internal data bus scki32 figure c.2 (d) port 4 block diagram (pin p4 0 )
405 c.3 block diagram of port 5 p5 n v cc v cc pucr5 n internal data bus pmr5 n pdr5 n pcr5 n sby wkp figure c.3 port 5 block diagram
406 c.4 block diagram of port 6 p6 n v cc v cc pucr6 n pdr6 n internal data bus pcr6 n sby figure c.4 port 6 block diagram
407 c.5 block diagram of port 7 p7 n v cc pdr7 n internal data bus pcr7 n sby figure c.5 port 7 block diagram
408 c.6 block diagrams of port 8 p8 0 v cc pdr8 n internal data bus pcr8 n sby v ss pdr8: pcr8: port data register 8 port control register 8 figure c.6 port 8 block diagram (pin p8 0 )
409 c.7 block diagrams of port 9 p9 n pdr9 n pmr9 n sby v ss pdr9 : n= 1 or 0 port data register 9 pwm module pwm n+1 internal data bus figure c.7 (a) port 9 block diagram (pins p9 1 and p9 0 ) p9 n pdr9 n sby v ss pdr9: n= 5 to 2 port data register 9 internal data bus figure c.7 (b) port 9 block diagram (pins p9 5 to p9 2 )
410 c.8 block diagram of port a pa n v cc pdra n internal data bus pcra n sby figure c.8 port a block diagram
411 c.9 block diagram of port b pb n internal data bus amr3 to amr0 a/d module v in n = 3 to 0 dec figure c.9 port b block diagram
412 appendix d port states in the different processing states table d.1 port states overview port reset sleep subsleep standby watch subactive active p3 7 to p3 1 high impedance retained retained high impedance * retained functions functions p4 3 to p4 0 high impedance retained retained high impedance retained functions functions p5 7 to p5 0 high impedance retained retained high impedance * retained functions functions p6 7 to p6 0 high impedance retained retained high impedance retained functions functions p7 7 to p7 0 high impedance retained retained high impedance retained functions functions p8 7 to p8 0 high impedance retained retained high impedance retained functions functions p9 5 to p9 0 high impedance retained retained high impedance * retained functions functions pa 3 to pa 0 high impedance retained retained high impedance retained functions functions pb 3 to pb 0 high impedance high impedance high impedance high impedance high impedance high impedance high impedance note: * high level output when mos pull-up is in on state.
413 appendix e list of product codes table e.1 h8/3802 series product code lineup product type product code mark code package(hitachi package code) h8/3802 h8/3802 mask rom hd6433802h hd6433802 ( *** ) h 64-pin qfp (fp-64a) series versions hd64433802fp hd6433802 ( *** ) fp 64-pin lqfp (fp-64e) hd6433802p hd6433802 ( *** ) p 64-pin dilp (dp-64s) ztat hd6473802h hd6473802h 64-pin qfp (fp-64a) versions hd6473802fp hd6473802fp 64-pin lqfp (fp-64e) hd6473802p hd6473802p 64-pin dilp (dp-64s) h8/3801 mask rom HD6433801h HD6433801 ( *** ) h 64-pin qfp (fp-64a) versions HD6433801fp HD6433801 ( *** ) fp 64-pin lqfp (fp-64e) HD6433801p HD6433801 ( *** ) p 64-pin dilp (dp-64s) h8/3800 mask rom hd6433800h hd6433800 ( *** ) h 64-pin qfp (fp-64a) versions hd6433800fp hd6433800 ( *** ) fp 64-pin lqfp (fp-64e) hd6433800p hd6433800 ( *** ) p 64-pin dilp (dp-64s) note: for mask rom versions, ( *** ) is the rom code.
414 appendix f package dimensions dimensional drawings of h8/3802 series packages fp-64a, fp-64e, and dp-64s are shown in figures f.1, f.2, and f.3 below. hitachi code jedec eiaj weight (reference value) fp-64a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 0.10 0.15 m 17.2 0.3 48 33 49 64 1 16 32 17 17.2 0.3 0.35 0.06 0.8 3.05 max 14 2.70 0 ?8 1.6 0.8 0.3 *0.17 0.05 0.10 +0.15 ?.10 1.0 *0.37 0.08 0.15 0.04 figure f.1 fp-64a package dimensions
415 hitachi code jedec eiaj weight (reference value) fp-64e conforms 0.4 g unit: mm *dimension including the plating thickness base material dimension m 12.0 0.2 10 48 33 116 17 32 64 49 *0.22 0.05 0.08 0.5 12.0 0.2 0.10 1.70 max *0.17 0.05 0.5 0.2 0 8 1.0 1.45 0.10 0.10 1.25 0.20 0.04 0.15 0.04 figure f.2 fp-64e package dimensions
416 hitachi code jedec eiaj weight (reference value) dp-64s conforms 8.8 g unit: mm 0.25 + 0.11 0.05 0 15 1.78 0.25 0.48 0.10 0.51 min 2.54 min 5.08 max 19.05 57.6 58.5 max 1.0 1 33 32 64 17.0 18.6 max 1.46 max figure f.3 dp-64s package dimensions
h8/3802 series hardware manual publication date: 1st edition, november 1999 2nd edition, january 2001 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 1999. all rights reserved. printed in japan.

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